Minutes SV-AC 02/13/03 Written by: Stephen Meier ATTN: Next SV-AC Meeting Feb 20th 9:30-11AM PST Dial-In = 888-830-6260 Intl: 1-505-242-2420 PartID = 908704 Legend: x = attended - = missed r = represented . = not yet a member v = valid voter (3 out of last 4) n = not valid voter v[xxxxxxxxxxx----x.] Faisal Haque (Cisco, Chairman) v[xxxxxxxxxxx-x-x-x] Steve Meier (Synopsys, Co-Chair) v[xxxxxxxxxx-xxx--x] Roy Armoni (Intel) v[xxxxxxx-x-xxxrxx.] Surrendra Dudani (Synopsys) v[xxxxxxxxxxxxxrxrx] Cindy Eisner (IBM) v[xxxxxxxxrxx-xxx..] John Havlicek (Motorola) v[-xxxxxx-xx-xxxxx.] Richard Ho (0-in) v[xxx-xxxxxxxxxxrx-] Adam Krolnik (LSI) v[xx-xxxxxxxxx---xx] Joseph Lu (Sun) v[xxxxxxxxxxx--xxxx] Erich Marschner (Cadence) v[x-xxxx-x-xxxxxx-x] Andrew Seawright (0-in) v[xxxxxxxxxx-xrxxxx] Bassam Tabbara (Novas) v[xxx-x-xxxxx-xxxx-] Prakash Narain (Real Intent) v[xxxx.............] Tej Singh (Mentor) v[xxx..............] Connie O'dell (Consultant) v[xx-x--xxx-x--xx-x] David Lacey (HP, OVL Chairman) n[-xx-xxx-rx-xxxrrx] Harry Foster (Verplex) n[--xx-----xxxxxxx.] Ambar Sarkar (Paradigm Works) n[----xxxxx........] Yaron Wolfsthal (IBM) n[---x.............] Glenn Wesley (Consultant) n[xx---x...........] Hillel Miller (Motorola) n[-----xxx-xxxxxxxx] Gail Dagan (Intel) n[------xxxxxxxxxx-] Rajeev Ranjan (Real Intent) n[-------x.........] Sagi Katz (Gallileo) n[------xxxx-x-x...] Richard Stolzman (Verplex) n[-----xxx-xxxxxxrx] Tom Fitzpatrick (Synopsys) n[-----x--x-x-x--xr] Tom Anderson (0-in) n[----------------x] Jason Andrews (Axis) ==|||||||||||||||| ==|||||||||||||||+- 07/09/02 ==||||||||||||||+-- 07/25/02 ==|||||||||||||+--- 08/01/02 ==||||||||||||+---- 08/08/02 ==|||||||||||+----- 08/15/02 ==||||||||||+------ 08/22/02 ==|||||||||+------- 09/05/02 ==||||||||+-------- 09/12/02 ==|||||||+--------- 09/19/02 ==||||||+---------- 09/26/02 ==|||||+----------- 10/03/02 ==||||+------------ 10/31/02 ==|||+------------- 12/03/02 ==||+-------------- 01/23/03 ==|+--------------- 01/30/03 ==|+--------------- 02/06/03 ==+---------------- 02/13/03 1. Review Process Faisal updated that review process will be updated to focus only on technical problems and semantic issues, corner cases. Faisal would like to avoid discussion of stylistic preferences within SVAC and leaves to consideration by the DWG which has charter to define the unified assertion kernel. Vassilios further clarified that the DWG has met for 6 months and discussed many of the issues that are being discussed on email reflectors. 2. New Issues Discussion on property directives layer: Erich had started discussion by email. Issue: Sem3: initial and never are allowed to co-occur, but are not compatible, 2nd John, 3rd Cindy Issue: Sem4: always is implicit only (not explicit), 1st Cindy, 2nd by Erich, 3rd by Adam Issue wrt. Sem1: right hand side of sequence implication provides nesting Discussion on nesting of sequence implication. There are issues which require sequence implication to provide sampling. Declaration of variables with sampling at same place is driving the requirement for a nested sequence implication. Some members indicated that this association may not be required. Issue: Sem5: new variable, 1st Erich, 2nd Cindy, 3rd John Bassam suggested an additional variable which can be per instance of properties and can be assigned and referenced by multiple attempts. Erich will create proposal. Discussion on local variables on whether there should be multiple assignments supported. Steve and Surrendra clarified that single assignment with declaration is clearest and then all evaluation paths have same variable with same value. Bassam explored if there is opportunity to have single variable handle that can be read from within path of evaluation. Issue: Syn6 Cindy, Erich, Adam Sequence operator syntax proprosal as defined by Cindy, Roy. Action: Cindy is concerned on whether the syntax parsable by a Yacc like parser. All agree that SV needs to be defined LALR1 grammer. All agree that this is a requirement for overall SystemVerilog. Group would like more clarity effort (possibly by Stefan Boyd) define and prove the BNF. Steve took action to get more details on this. Issue: Syn7 Removed named boolean expression. Cindy, Erich, Adam Discussion on the merits and differences. Steve and Surrendra indicated the boolean is parameterized, consistent with sequence and properties and sampled items. Cover discussion ================= Discussion on cover construct. Cindy raised concern on why property is allowed for cover and suggested to restrict to just sequence. Other raised concern on vacuous successes of sequence and whether they should be filtered out. Right now the LRM does not define specific semantics. John indicated that there is a very rich set of capabilities that a tool can define and implement. Agree to define primitive capabilities for boolean and sequences and properties. Adam is interested in filtering out vacuous successes from action block. Concerns from Erich, and John that it is hard to define simply whether it is vacuous or not. Cindy discusses defined rules for vacuity. Cindy stated requirement that basic users should not get 100% coverage when they always have reset causing vacous success of their properties. Action: Surrendra will write semantic description of basic primitives (sequences, booleans). He will work with Bassam to review. Scheduling Discussion ===================== Erich asserted that it is important for assertions to be written on both testbench and design and on a mixture of the two. Steve updated that there is a scheduling semantic working group which is working ernestly to meet these requirements. It is noted for the record that assertions should be applicable for both testbench and design and mixture of variables from both. Procedural scheduling ===================== Prakash indicated that he is open to removing check construct but would like to propose that the hole of checking behaviors that occur immediately during simulation. He proposes that scheduling be different for combinational blocks versus sequential blocks. Issue: Sem1 {11.4} Sequential Implication: Cindy, Erich, John John and Surrendra submitted proposals. John indicated that they both achieve the same effect of moving to the higher level (above sequences). Surrendra walked through his proposal. Cindy expressed concern that the proposal supports nesting and this is the first time there is notion of formula layer (nesting above sequences). We reviewed example of nesting (Adam's issue) in which the nesting is used to provide mechanism for sampling of the variable. Bassam indicates concern of too much expressiveness with nesting that may allow for properties to be created that are overly complex and too hard to understand. Discussion on asscociativity, clarified that it is right associativity and the syntax provides for explicit use of () for explicit association. The intent to not allow left association ? All agree to have at least the sequence_expr => sequence_expr at the top level. Open issue: Whether to support sequence_expr => prop_expr (i.e.) nesting. Actions: Surrendra will provide an example and description of nesting Members will review syntax and prepare proposal if there are alternate proposals to be due by Monday. Issue: Sem2 Remove check construct, Owner = Adam Prakash has concerns that there are some corners which only this functionality can support. Prakash will provide justification examample by email by Friday. Issue will be voted by email Monday. Issue: Syn1 Remove unary delay, Owner = Cindy Cindy discussed a potential proposal with John to preserve unary delay, but remove binary delay. The idea is to have the meaning the same whether the parantheses are used or not. Standalone leading [0] would be explicitly not allowed. Surrendra proposal was provided which Cindy awknowleges meets the desire of her issue. Surrendra indicates that it removes unnecessary parantheses. Erich indicated that it does not provide for leading delay. The proposal provides for parameterized delays of any non-zero integer value wherever delays appear. Cindy will prepare a proposal following John's suggestions by Sunday. Issue: Syn2 Replace seq by sequence Decision to have sequence, no objections. 2) New Issues {11.4} true as keyword by Adam, 2nd by John, 3rd by Cindy, 4th by Bassam Unnecessary keyword - all agree to remove. {11.6.3, 11.6.5} change and, or and intersect to &, |, && by Cindy Cindy feels that and, or are ugly and suggest using existing boolean operators in verilog. Surrendra indicates that or and and are already keywords. Steve indicated that there would be hard to understand and distinguish the boolean operators from the sequence operators. Also proposal for && for and, | for or and & for intersect. Roy indicates & has different precedence in verilog. Bassam indicates that style should be consistent either all characters or all keywords but not a mix of both. Steve expressed strong concern on DWG process for language design should be basis for review and SV-AC should not undertake language design from first principles. {11.6.8} Addition of non-overlapping sequence implication (->) by Cindy, second Erich, third John See email by Cindy. She suggests sequence implication to allow operator to have an operator (i.e. ->) in which the left operator starts one cycle later than the match of the right operator. Others indicated that there may not be sufficient need as the form can be achieved by starting a sequence by "1 ; ". 3) Review of document {11.9} System Tasks Steve indicated document is in process of update with DAS v1.0 system functions. {11.10} Property definition Erich suggested that property directives should be provided at the property level. Cindy suggsted that always be made explicit and require user to invoke one of them as opposed to having an implicit always. {11.11) Property instantiation in module There was clarification that properties can be instantiated in module as well as instances. Action is to update the document with explicit clarification on where property, sequence delcarations can be made. Review concluded at Sec 11.11 Meeting Concluded