Minutes SV-AC 01/30/03
Written by: Stephen Meier

ATTN: Next SV-AC Meeting Feb 6th 9:30-11AM PST 
	Dial-In = 888-830-6260
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Legend:
x = attended
- = missed
r = represented
. = not yet a member
v = valid voter (3 out of last 4)
n = not valid voter

v[xxxxxxxxx----x.] Faisal Haque (Cisco, Chairman)
v[xxxxxxxxx-x-x-x] Steve Meier (Synopsys, Co-Chair)
v[xxxxxxxx-xxx--x] Roy Armoni (Intel)
v[xxxxx-x-xxxrxx.] Surrendra Dudani (Synopsys)
v[xxxxxxxxxxxrxrx] Cindy Eisner (IBM)
v[x-xxx-rx-xxxrrx] Harry Foster (Verplex)
v[xxxxxxrxx-xxx..] John Havlicek (Motorola)
v[-xxxx-xx-xxxxx.] Richard Ho (0-in)
v[x-xxxxxxxxxxrx-] Adam Krolnik (LSI)
v[-xxxxxxxxx---xx] Joseph Lu (Sun)
v[xxxxxxxxx--xxxx] Erich Marschner (Cadence)
v[xxxx-x-xxxxxx-x] Andrew Seawright (0-in)
v[xxxxxxxx-xrxxxx] Bassam Tabbara (Novas)

n[x-x-xxxxx-xxxx-] Prakash Narain (Real Intent)
n[xx-----xxxxxxx.] Ambar Sarkar (Paradigm Works)
n[-x--xxx-x--xx-x] David Lacey (HP, OVL Chairman)
n[--xxxxx........] Yaron Wolfsthal (IBM)
n[xx.............] Dage Singh (Mentor)
n[x..............] Connie O'dell (Consultant)
n[-x.............] Glenn Wesley (Consultant)
n[---x...........] Hillel Miller (Motorola)
n[---xxx-xxxxxxxx] Gail Dagan (Intel)
n[----xxxxxxxxxx-] Rajeev Ranjan (Real Intent)
n[-----x.........] Sagi Katz (Gallileo)
n[----xxxx-x-x...] Richard Stolzman (Verplex)
n[---xxx-xxxxxxrx] Tom Fitzpatrick (Synopsys)
n[---x--x-x-x--xr] Tom Anderson (0-in)
n[--------------x] Jason Andrews (Axis)
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1. Issue Discussion on Sec 11.1 - 11.6.8

Issue1 {11.4} : Cindy, Erich, John

Cindy proposed that the unary delay feature be removed and only allow the delay to occur when directly following the sequence concatentation operator ";".  Delays can be passed within the sequence element by using true*[range].  Steve indicated that there was no lost functionality, just a syntax sugaring for flexibility.  No proposal required as it is a deletion.


{11.4} [BT] Bassam proposed using a delay syntax that is different from ";".  He proposed using the Verilog delay character "#" and that when it occurs in a delay context its interpretation would be a cycle delay.  Lots of discussion on DWG dialog.  Second by Surrendra, no third.

{11.4} [AS] Adam asked if examples on page 46 are correct in the numbe of trues.  Steve indicated that they were correct.  Discussion went on related to Issues1 and the fact that the () change interpretation of leading delay.

Issue2: {11.6.8} John expressed concern on sequence implication and context dependence.  The issue is that a match on a prefix does not assure a match on the entire word.  This behavior is distinct from all other sequences.  John is proposing to move sequence implication to the property level.  Roy indicated that some work would be needed to ensure closure of the properties and that level.  Issue created, John owes specific proposal.
2. Requirements Status

Steve walked through assertionRequirements3.1_status4.xls document which updates
the SV-AC on current view of the working document Rev 0.79.

{11.6.9} [JH] John and others suggested that we simplify the throughout restriction.  Steve indicated that the text was in error and that document would be updated to support
boolean_expr throughout sequence_expr.  All agreed to this change.

Issue3 {11.5} [AK] Second by Harry, Cindy, Andrew

Adam suggests that seq be replaced by sequence as keyword.  Issue created, proposal is clear.

Issue4 {11.2} [AK] Second by Bassam, Erich

Immediate check statements are too restrictive to motivate their existence.  The only differences from Verilog boolean checks are that
a) omission of the else gives implicit $error system task call
b) pass/fail statements for taking action on failure
c) explicit check as a documentation difference

no proposal required as this is deletion.

2) Review of document

{11.6.10} [AK] action for Steve to update document to indicate that the limit is inclusive of the endpoint of containing sequence_expr2.

{11.7} [AK] Adam questioned the need for a new type just for assertions and how it can be justified.  Surrendra replied that the booleans are always converted to 0,1 in the assertion context when associated with sampling clock.  Additionally the $past and $rose system functions can be included in the expression.

{11.8} [Lots of discussion]  As Steve walked through local variables there was clarification on the scope of variables.  It was additionally clarified that there can only be a single assignment to the variable and that overriding a variable assignment is not supported.  Several AC members indicated interest in additional features such as reference to variables from outside of scope by hierarchical reference and ability to have multiple assignments to variables.  Steve indicated that these requriements all make the local variable much more complex in design and implementation due to concurrent evaluation of assertions with multiple paths and multiple attempts.  It is quite a challenge to have a name reference to a specific path of assertion evaluation.  Adam indicated a concern that the functionality of named sequences is not as useful because there is no way to refer to variables assigned within the named sequences.

Review concluded at Sec 11.8

3) Voting process

Faisal indicated that issues would be reviewed within DWG and proposed resolution would be communicated at next SV-AC meeting.


Meeting Concluded