Minutes SV-AC 12/02/2002
Written by: Steve Meier

ATTN: Next SV-AC Meeting Dec 12 9-11AM PST 
	Toll Free Dial In Number: (888)422-7101 
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	PARTICIPANT CODE: 419923 

Legend:
x = attended
- = missed
r = represented
. = not yet a member

[xxxxxxx----x.] Faisal Haque (Cisco, Chairman)
[xxxxxxx-x-x-x] Steve Meier (Synopsys, Co-Chair)
[-xxx-xxxxxxrx] Tom Fitzpatrick
[-x--x-x-x--xr] Tom Anderson (0-in)
[------------x] Jason Andrews (Axis)
[xxxxxx-xxx--x] Roy Armoni (Intel)
[-xxx-xxxxxxxx] Gail Dagan (Intel)
[---x-x--xxxxx] Simon Davidmann (Synopsys)
[xxx-x-xxxrxx.] Surrendra Dudani (Synopsys)
[xxxxxxxxxrxrx] Cindy Eisner (IBM)
[------xxrrrxx] Peter Flake (Synopsys)
[xxx-rx-xxxrrx] Harry Foster (Verplex)
[xxxxrxx-xxx..] John Havlicek (Motorola)
[xxx-xx-xxxxx.] Richard Ho (0-in)
[---x.........] Sagi Katz (Gallileo)
[xxxxxxxxxxrx-] Adam Krolnik (LSI)
[--xxx-x--xx-x] David Lacey (HP, OVL Chairman)
[xxxxxxxx---xx] Joseph Lu (Sun)
[xxxxxxx--xxxx] Erich Marschner (Cadence)
[-x...........] Hillel Miller (Motorola)
[------------x] Paul Menchini (Menchini & Associates)
[x-xxxxx-xxxx-] Prakash Narain (Real Intent)
[--xxxxxxxxxx-] Rajeev Ranjan (Real Intent)
[-----xxxxxxx.] Ambar Sarkar (Paradigm Works)
[--xxxx-x-x...] Richard Stolzman (Verplex)
[xx-x-xxxxxx-x] Andrew Seawright (0-in)
[xxxxxx-xrxxxx] Bassam Tabbara (Novas)
[xxxxx........] Yaron Wolfsthal (IBM)
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1. Status Update

Faisal updated the group on DWG progress.   He indicated that
the DWG has made decisions on core language features and semantics,
which are reflected in the 0.75 document.  The document demonstrates
the feature set and semantics. The syntax is still open and
only in document to demonstrate features as example syntax.

Clarification on Rev 0.75 document include:

Sec 11.10: the assume, restrict directives and reset condition will be removed

Sec 11.12: this entire section will be removed

Faisal indicated the schedule moving forward is for the DWG to make
decision on syntax and deliver complete working document to SV-AC.  From
there the SV-AC will review the working document section by section and
drive towards the LRM draft.

2. Document Review

Steve walked through Rev 0.75 of working document.  
Comments are by section and intials {sec}[XX]

{11.2}
[BT] Clarification on whether the immediate assertions are the same semantically
as DAS v1.0.  The intention is to have the same semantic.  Bassam requested that
document include same documentation as in the original SV v3.0 LRM [Action=Steve].

[AK] Are there any restriction on pass/fail action blocks ?  Steve indicated that
restrictions will be made on these blocks to restict them to only verification code.
Details on these restrictions still need to be spelled out in document [Action=Steve]

{11.4}
[AK] Comment on requirement for named event declaration.  Adam noted that most
common usage will likely be in-line within either sequence or property declaration.

{11.7}
[AK] Adam questioned the delay syntax and whether the ; separator advances time
to next cycle.  Steve clarified that in Rev0.75 of document the separator does
not pass time.  Erich and Steve indicated that syntax was still under discussion
and we are working to get best consistency and utility. [Action=DWG]

{11.7.6} 
[AK] Adam raised concern about consistency with SV-EC constrains proposal which
is using => for implication, while the DWG document is using if. Faisal
indicated that he would review synchronization with SV-EC.  [Action=Faisal]

{11.8}
[AK]  Adam raised concern about need for boolean variables when there is already 'define
feature in Verilog.  Erich indicated that these are parameterized, yet Adam indicated
that Verilog support parameters as well.  Steve indicated that they are sampled
by sampling clock.

{11.9}
[AK] Adam asked if the DAS v1.0 boolean operation utility system tasks like $onehot will be included.  Steve said yes.  [Action=Steve]

{11.10}
[AK] Adam expressed concern on requirement for initial directive.  Steve indicated that he heard from users desire to have property that when invoked would be evaluated only once (one hot mux).

[AK] Adam expressed concern about not having assume directive.  Steve and Prakash indicated that the DWG discussed this and did not find consistent tool interpretation of semantics of assume.  So asserts can be used to define assumptions and tool directives will be needed to direct various tool implementations.

[EM & PN] Concern on cover directive for properties and fail action block when used with cover directive.  [Action=DWG]

{11.10.1}
[AK] Adam indicated desire to see restrictions on where properties can be declared.  He would like to see them restricted to appear only outside of procedural code.

{11.11}
[AK]  Adam questioned why there was need to define direction of the signals on template declaration. Further clarificaiton is needed [Action=Steve]

3. Discussion on Process

Steve indicated there would be a structured review process after the DWG brings the full proposal to SV-AC.  There will be need to have quorum of multiple members to raise an issue for consideration.  Sementic problems will be resolved once identified.

It was suggested that effort be made to write the FVTC examples to validate the language.  [Action= Faisal]

Yaron expressed concern on timetable for SV-AC.  He indicated that semantics definition and resolution of issues has required 6 months and is still under review.  Steve offered that past efforts to define PSL semantics and OVA semantics could be leveraged to speed the process.


Adam expressed interest in resolution of overlap areas with SV-EC.  Examples of this is the set membership operators from constraints proposal which Adam would find useful with asseritons.  [Action = Faisal]


{11.7.8}
[AK] Adam indicated that he likes the various options to use lengths of sequences and suggested further completness on the set.

Meeting Concluded