Re: [sv-ac] Call to vote: Due March 14

From: ben cohen <hdlcohen@gmail.com>
Date: Wed Mar 09 2011 - 20:01:37 PST

2804 has argument passing issues:
The checker has 7 arguments. *When it is instanced, only 6 actuals are
passed.*
*
*
checker clocking_example ( logic sig1,sig2,*default_clk*,rst,
event e1,e2,e3 );
...

clocking_example c1 (s1,s2,rst,
  posedge clk1 or posedge clk2,
  posedge clk1,
  negedge rst);

We need this instead:
clocking_example c1 (s1,s2,*default_clk, *rst,
  posedge clk1 or posedge clk2,
  posedge clk1,
  negedge rst);

On Wed, Mar 9, 2011 at 11:21 AM, Korchemny, Dmitry <
dmitry.korchemny@intel.com> wrote:

> -You have until 11.59 pm PDT, Wednesday, March 14, 2011 to respond
>
> -An issue passes if there are zero NO votes and half of the eligible
>
> voters respond with a YES vote.
>
> -If you vote NO on any issue, your vote must be accompanied by a reason.
>
> The issue will then be up for discussion during a future conference
>
> call.
>
>
>
> As of the March 8, 2011 meeting, the eligible voters are:
>
> Ashok Bhatt
>
> Laurence Bisht
>
> Eduard Cerny
>
> Ben Cohen
>
> Tapan Kapoor
>
> Scott Little
>
> Manisha Kulshrestha
>
> Anupam Prabhakar
>
> Erik Seligman
>
> Samik Sengupta
>
> Tom Thatcher
>
>
>
> Mantis 2476 ____ Yes ____ No
>
> http://www.verilog.org/mantis/view.php?id=2476
>
> http://www.eda-stds.org/mantis/file_download.php?file_id=4828&type=bug
>
>
>
> Mantis 2804 ____ Yes ____ No
>
> http://www.eda-stds.org/svdb/view.php?id=2804
>
> http://www.eda-stds.org/mantis/file_download.php?file_id=4830&type=bug
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Received on Wed Mar 9 20:02:32 2011

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