Re: [sv-ac] New proposals uploaded for 2804 and 2476

For 2476, page 5, bottom of page,
The control_bits argument to $countbits is not required to be a compile-time
constant
[Ben] control_bits needs a different font (courier), same font as on top of
page 5 for control_bits
-----------------------
For 2804, page 1
1) The event expression consists solely of an event variable, consists solely
of a clocking block event, or is of the form edge_identifier expression1 [
iff expression2 ] and is not a proper subexpression of an event expression
of this form.
[Ben] Too many consists. Change to
1) The event expression consists solely of an event variable, solely of a
clocking block event, or is of the form edge_identifier expression1 [ iff
expression2 ] and is not a proper subexpression of an event expression of
this form.

Page 2
 Assertion p1a will be clocked by posedge default_clk. This is because
after the substitution of the actual argument posedge clk1 or posedge clk2
for the formal argument e1, it does not satisfy the clock inference
conditions in 16.15.6. If clocking based on e1 is desired, it must be done
explicitly as in property p1b.
[Ben] It would be good to explain which rule is indeed violated. For this
case:
 Assertion p1a will be clocked by posedge default_clk. This is because
after the substitution of the actual argument posedge clk1 or posedge clk2
for the formal argument e1, it does not satisfy the clock inference
conditions in 16.15.6, *particularly condition "b". *If clocking based on
e1 is desired, it must be done explicitly as in property p1b.

Assertion p2a will be clocked by posedge clk1. This is because the event
control of p2_block satisfies the conditions in 16.15.6 after the formal
arguments are substituted with the actual arguments.
[Ben] Assertion p2a will be clocked by posedge clk1. This is because the
event control of p2_block satisfies the conditions in 16.15.6, *
particularly condition "c2", * after the formal arguments are substituted
with the actual arguments.

Assertion p3a will be clocked by posedge default_clk. This is because the
event control of p3_block does not satisfy the conditions in 16.15.6.
[Ben] Assertion p3a will be clocked by posedge default_clk. This is because
the event control of p3_block does not satisfy the conditions in
16.15.6, *particularly
condition "c2". *
*[Ben] I am open to other qualifiers, but it would be more useful to the
reader if the specific rules that apply or are violated are identified. *
*
*
*Ben Cohen *

On Wed, Feb 23, 2011 at 10:25 AM, Seligman, Erik <erik.seligman@intel.com>wrote:

> I edited the proposals based on yesterday’s SV-AC discussions.
>
>
>
> http://www.verilog.org/mantis/view.php?id=2476
>
> http://www.verilog.org/mantis/view.php?id=2804
>
>
>
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