[sv-ac] Minutes from SV-AC Meeting: 2/8/2011

Minutes of SV-AC Meeting
Date: 2011-02-08
Time: 16:30 UTC (8:30 PST)
Duration: 1.5 hours

Dial-in information:
--------------------
Meeting ID: 38198

Phone Number(s):
1-888-813-5316 Toll Free within North America

Live Meeting: https://webjoin.intel.com/?passcode=6080259

Agenda:
-------
- Reminder of IEEE patent policy.
See: http://standards.ieee.org/board/pat/pat-slideset.ppt

- Minutes approval

- F2F

- Email ballot results
2804 passed

- New issues

- Issue resolution/discussion

Addressing champions' feedback
3113: Add port_identifier to constant_primary BNF for sequences,
properties and checkers
2476: Need clarification about system functions $onehot, etc
2412: Allow clock inference in sequences
2938: Surprising (to some users) interaction between deferred assertions
& short-circuiting

3135: Verbal explanation of nexttime and always is misleading for
multiple clocks

- Enhancement progress update
2328: Review and relax restrictions on data types in assertions

- Opens

Attendance Record:
------------------
          Legend:
                  x = attended
                  - = missed
                  r = represented
                  . = not yet a member
                  v = valid voter (2 out of last 3 or 3/4 overall)
                  n = not a valid voter
                  t = chair eligible to vote only to make or break a tie

Attendance re-initialized on 2010-07-06:

   v[xxx...........................] Ashok Bhatt (Cadence)
   v[xxx-xxx-xxxxxxxxx-x-xxxxx--xxx] Laurence Bisht (Intel)
   v[xx-xxxxxxxxxxxx-xxxxxxxxxxxxx-] Eduard Cerny (Synopsys)
   v[---xxx--x-xxxxxxx-xxxxx-xxxxxx] Ben Cohen
   n[-----------xx-x-xxx-x--xxxxxxx] Surrendra Dudani (Synopsys)
   n[x----x-x-x--xx---xxxx---x-xxxx] Dana Fisman (Synopsys)
   n[---------xxxxx-xxxx-x-xxxxxxxx] John Havlicek (Freescale)
   v[xxxxxxxxxxxxx-xxx-xxxxxxxxxxxx] Tapan Kapoor (Cadence)
   t[xxxxxxxxxxxxx--xxxxxxxxxxxxxxx] Dmitry Korchemny (Intel ¿ Chair)
   v[xxxxxxxxxxxxx--xxxxxx-xxxxxxxx] Scott Little (Freescale)
   v[xxxxxxxxxxxx-xxxxxxxxx-xxxxxxx] Manisha Kulshrestha (Mentor Graphics)
   v[xxxxxxxxxx-xxxxxxxxxxxxxxxxxxx] Anupam Prabhakar (Mentor Graphics)
   v[-xxx--x-xx-xxx-xx--xxxxxxx-xxx] Erik Seligman (Intel)
   v[xxx-xxxx-xxxx--xxxxxx-xxxxxxx.] Samik Sengupta (Synopsys)
   v[xxxxxxxxxxxx-xxxxxxxxxxxxx-xxx] Tom Thatcher (Oracle ¿ Co-Chair)
   n[x-------x.....................] Srini Venkataramanan (CVS Pvt)
     |- attendance on 2011-02-08
   |--- voting eligibility on 2011-02-08

Minutes:
--------
- Reminder of IEEE patent policy.
See: http://standards.ieee.org/board/pat/pat-slideset.ppt
Participants were reminded of the IEEE patent policy.

- Minutes approval
Ed: Move to approve minutes
Samik: Second
        Vote results: 9y, 0n, 0a

(Manisha Joined)

- F2F
Dmitry: Nobody has volunteered to host. Still looking for somebody to host.

- Email Ballot results:
2804 passed

(Scott joined)
Dmitry: Friendly amendment was to replace comma with semicolon.
Tom: Semicolon correct in this context because the two clauses it joins are
        complex.

Lawrence: E-mailed a question about an example
Tom: There is no positional dependence for the clocking event?
Dmitry: No, not according to these rules.
Manisha: An example would be a good idea.
Anupam: Clock inference is kind of an exception.
        Every other construct within a checker is substituted then elaborated.
        These rules for clock inference are the only case where processing
        occurs before substitution.

Dmitry: Suggest we defer to next week when Erik will be here.

- Issue resolution/discussion

Addressing champions' feedback
3113: Add port_identifier to constant_primary BNF for sequences,
properties and checkers
Dmitry: Will call for an e-mail ballot.

2476: Need clarification about system functions $onehot, etc
Dmitry: Erik not here.

2412: Allow clock inference in sequences
Ed: When using $inferred_clock, the inference is done at the point
        of the instance. Isn't that incompatible with new inference?
Anupam: Sampled-value functions infer clock after inlining.
Anupam: Current rules: In sequences and properties, clock inferences occur
        after inlining, while in modules & interfaces, clock inferences occur
        at point of instance.
Ed: Should we change definiton of $inferred_clock to work after inlining?
        Seems like we have two different sets of rules for inference.

Ed's example:
        default clocking cc @(posedge clk3); endclocking
        property p(clk=$inferred_clock, clk1, x);
                @clk a ##1 @clk1 x ##1 @clk x;
        endproperty
        assert property (p(,z,$rose(b));

        The $inferred_clock in the property would get @(posedge clk3)
        The inferred clock for $rose will be inferred after inlining,
            and thus would get z

Anupam: But any change to make things consistent would make things backward-
        incompatible.

3135: Verbal explanation of nexttime and always is misleading for
multiple clocks
Dana: Shalom noted that this explanation did not cover "eventually"

Dmitry: Will call for an e-mail ballot.

- Enhancement progress update
2328: Review and relax restrictions on data types in assertions

Scott: Has modified proposal.
Dmitry: String types forbidden, but what about string literals.
Dmitry: String literals should be allowed.

Dmitry: There are Mantis items regarding adding dynamic types to assertions.
Scott: Do we want to attack this in this PAR? If so, that should all be
        in this proposal.
Ed: If we allow dynamic types, then we will have to deal with sampling
Ed: Can't sample $time and $realtime
Dmitry: Should we vote on this?
Scott: Let's wait to next time.

Meeting adjourned.

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