[sv-ac] Minutes of SV-AC Meeting 2/1/2010

Minutes of SV-AC Meeting
Date: 2011-02-01
Time: 16:30 UTC (8:30 PST)
Duration: 1.5 hours

Dial-in information:
--------------------
Meeting ID: 38198

Phone Number(s):
1-888-813-5316 Toll Free within North America

Live Meeting: https://webjoin.intel.com/?passcode=1344341

Agenda:
-------
- Reminder of IEEE patent policy.
See: http://standards.ieee.org/board/pat/pat-slideset.ppt

- Minutes approval

- Email ballot results
1933 passed
2412 failed

- New issues

- Issue resolution/discussion

Addressing champions' feedback
2804: Need to clarify rule (b) in 16.15.6 to allow inferred clock when
expression appears in procedural assertion
3113: Add port_identifier to constant_primary BNF for sequences,
properties and checkers
2476: Need clarification about system functions $onehot, etc
2412: Allow clock inference in sequences
2938: Surprising (to some users) interaction between deferred assertions
& short-circuiting

- Enhancement progress update
2328: Review and relax restrictions on data types in assertions

- Opens

Attendance Record:
------------------
          Legend:
                  x = attended
                  - = missed
                  r = represented
                  . = not yet a member
                  v = valid voter (2 out of last 3 or 3/4 overall)
                  n = not a valid voter
                  t = chair eligible to vote only to make or break a tie

Attendance re-initialized on 2010-07-06:

   n[xx...........................] Ashok Bhatt (Cadence)
   v[xx-xxx-xxxxxxxxx-x-xxxxx--xxx] Laurence Bisht (Intel)
   v[x-xxxxxxxxxxxx-xxxxxxxxxxxxx-] Eduard Cerny (Synopsys)
   v[--xxx--x-xxxxxxx-xxxxx-xxxxxx] Ben Cohen
   n[----------xx-x-xxx-x--xxxxxxx] Surrendra Dudani (Synopsys)
   n[----x-x-x--xx---xxxx---x-xxxx] Dana Fisman (Synopsys)
   n[--------xxxxx-xxxx-x-xxxxxxxx] John Havlicek (Freescale)
   v[xxxxxxxxxxxx-xxx-xxxxxxxxxxxx] Tapan Kapoor (Cadence)
   t[xxxxxxxxxxxx--xxxxxxxxxxxxxxx] Dmitry Korchemny (Intel ¿ Chair)
   v[xxxxxxxxxxxx--xxxxxx-xxxxxxxx] Scott Little (Freescale)
   v[xxxxxxxxxxx-xxxxxxxxx-xxxxxxx] Manisha Kulshrestha (Mentor Graphics)
   v[xxxxxxxxx-xxxxxxxxxxxxxxxxxxx] Anupam Prabhakar (Mentor Graphics)
   v[xxx--x-xx-xxx-xx--xxxxxxx-xxx] Erik Seligman (Intel)
   v[xx-xxxx-xxxx--xxxxxx-xxxxxxx.] Samik Sengupta (Synopsys)
   v[xxxxxxxxxxx-xxxxxxxxxxxxx-xxx] Tom Thatcher (Oracle ¿ Co-Chair)
   n[-------x.....................] Srini Venkataramanan (CVS Pvt)
     |- attendance on 2011-02-01
   |--- voting eligibility on 2011-02-01

Minutes:
--------
- Reminder of IEEE patent policy.
See: http://standards.ieee.org/board/pat/pat-slideset.ppt
Participants were reminded of the IEEE patent policy.

- Minutes approval
Eric: Move to approve minutes
Scott: Second
        Vote results: 7y, 0n, 0a

- Face-to-face:
Tom: Who will host?
Dmitry: Who will attend?
        Tom, Erik, Dmitry, Anupam, possibly Scott.

(Tapan and Manisha joined).

- Email ballot results
1933 passed
2412 failed

Discussion of 2412:
Scott: Assertion a2 should use matched, not triggered.
Anupam: Made the change.
Scott: Assertion a4 can use triggered.
Anupam: Made the change.
Tom: Shouldn't assertion a3 also use matched?
Anupam: There is a difference between a2 and a3:
        In a3, the clock is already changed before the e4.triggered, so
        triggered is ok here.
Tom: OK.
Ed: Disagree that sequence method e4.triggered infers clock clk_e2
        Shouldn't e4.triggered get its clock from point of instantiation?
        
Manisha: Does LRM state whether rewriting algorithm is applied before
        clock flow rules.
Anupam: If rewriting algorithm is applied before clock flow, then what we
        have is correct.

Tapan: Seems that different rules apply inside assertion or outside
assertion
Anupam: That was intentional.
Ed: Consistent with sampled value functions, which will not infer
        clock when used inside clocking or disable conditions.
Dmitry: It would be confusing for a clocking or disable expression to infer
        from the default clock.
Tapan: OK with that explanation.

Manisha: Annex F: F.2 Re-writing algorithm is applied before clock
        inferencing is applied.
Anupam: Given this, what we have now should be correct.
Ed: Need to think about this more carefully.
Dmitry: Other minor comments: comments in example should not be in bold.

Ed: In last example: checker is defined inside a module. This may be
        an unusual usage.
Manisha: In example, default clocking needs an endclocking.

- Issue resolution/discussion

Addressing champions' feedback
2804: Need to clarify rule (b) in 16.15.6 to allow inferred clock when
expression appears in procedural assertion

Erik: Added example. The example shows how clock inference is applied
        both before and after. If a clock can be inferred either time, then
        that clock will be the inferred clock.

3113: Add port_identifier to constant_primary BNF for sequences,
properties and checkers

Will discuss next week.

2476: Need clarification about system functions $onehot, etc

Dmitry: Adam Krolnik suggested consolidating, just using $countbits
function.
Tom: Comments seem to be unanimous in changing the "bit-shot" function.
Erik: Should we just move this to chapter 20, as people suggest?

Erik: Second question: Would these functions go in 20.13 with other
        Would other functions, like sampled-value functions also go in ch 20?

Meeting adjourned

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