Re: [sv-ac] New proposal posted for 2476 at http://www.verilog.org/mantis/view.php?id=2476

Three comments:
1) $bitshot (<expression>,<active_bits>,<quiet_bits>)
Do we want some defaults? For example:
$bitshot (<expression>,[<active_bits=1]>,[<quiet_bits=0>]) ??

2) $bitshot can be read as "$ bits hot" or as "$ bit shot". Obviously, we
mean *bits-hot* and not *bit-shot*. Somehow, it struck me as funny. Do we
care? Do we want an underscore, such as $bits_hot ??

3) In the above example, we have a vector myvec *which *is allowed to have
values 0, X, or Z on inactive bits during some design initialization phase,
but afterwards expected to only have 0 for inactive bits.
// Change the "which" to "that"
In the above example, we have a vector myvec *that *is allowed to have
values 0, X, or Z on inactive bits during some design initialization phase,
but afterwards expected to only have 0 for inactive bits.

Ben Cohen systemverilog.us

On Wed, Jan 26, 2011 at 12:06 PM, Seligman, Erik <erik.seligman@intel.com>wrote:

> The new version at http://www.verilog.org/mantis/view.php?id=2476 adds a
> bunch of clarifying examples, and tweaks some phrasings. Please take a look
> & see if the $bitshot function description seems clearer, or if further
> changes are needed. I have also emailed sv-bc to see if our current
> description of the expression arg will work.
>
>
>
> Once we have the basic content solid, we can look at Shalom’s suggestion to
> also move all this stuff into chapter 20.
>
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