[sv-ac] RE: arguments for system functions

From: Kulshrestha, Manisha <Manisha_Kulshrestha@mentor.com>
Date: Wed Nov 17 2010 - 22:53:18 PST

Hi Tapan,

It is not clear from the description if $onehot0 etc. have to follow the
same restrictions on the expression as in expressions in assertions.
Since these functions can be used outside of assertions, it is better to
describe what kind of arguments can be passed to them.

Manisha

-----Original Message-----
From: Tapan Kapoor [mailto:tkapoor@cadence.com]
Sent: Thursday, November 18, 2010 12:19 PM
To: Kulshrestha, Manisha; sv-ac@eda.org
Subject: RE: arguments for system functions

Hi Manisha,

The argument to these function is "expression", which is also an
argument to immediate assertions (16.3), deferred assertions (16.4) and
sampled value functions like $rose, $fell (deal with LSB of expression)
in section 16.9.3. These are also potential candidates if any definition
change is to be considered.

Section 16.6 does provide some sort of definition (which more of set of
restrictions) for the expression that can appear in sequence and
property expressions. I tend to agree that this definition is not good
enough for all the constructs (discussed in clause 16).

Warm regards,

Tapan

"You must be the change you want to see in the world" : Mahatma Gandhi

>-----Original Message-----
>From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
>Kulshrestha, Manisha
>Sent: Thursday, November 18, 2010 11:21 AM
>To: sv-ac@eda.org
>Subject: [sv-ac] arguments for system functions
>
>Hi,
>
>Currently LRM does not define what type of expressions can be used in
>system functions $onehot, $onehot0 etc. (these functions are defined in
>16.12.). Since the expression passed to these function should be
>converted to a bit vector before doing any analysis on it, is it OK to
>restrict the expression to be an integral type (6.11.1) ? Or probably
>that was the intension initially but never got documented.
>
>Comments ?
>
>Thanks.
>Manisha
>
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Received on Wed Nov 17 22:53:44 2010

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