[sv-ac] Re: [SV-AC] Local Variables Flow Out Issue in and/or/intersect/implies

Update the file in http://www.eda-stds.org/svdb/view.php?id=3195 , and
 Added:
"The local variable shall not be read in the same cycle it is written. "

[Ben] I believe that there would be a race condition because one property
can write a value to the local variable while a concurrent property reads
the property. For example:
property P_race;
  automatic int v;
    (a, v=data) ##[1:3] b) implies
    (c==v ##2 d): // This consequent may be processed before the antecedent.
endproperty :P_race

On Wed, Sep 1, 2010 at 6:47 PM, ben cohen <hdlcohen@gmail.com> wrote:

> However, there is a need to be able to set and read local variables in one
> sequence or property (the LHS), and to read those local variables in another
> sequence / property (RHS).
> Please see http://www.eda-stds.org/svdb/view.php?id=3195
> I uploaded a proposal.
> Ben Cohen
>

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