Re: [sv-ac] checker formal arguments may not be connected to interfaces // Updates

fchecker_v3.sv represents a model where the checker does not use any
modport.
This is another way of also using interfaces.
Ben

On Fri, Aug 27, 2010 at 9:28 PM, ben cohen <hdlcohen@gmail.com> wrote:

> http://www.eda-stds.org/svdb/view.php?id=2751
> <http://www.eda-stds.org/svdb/view.php?id=2751> File mantis2751.pdf
> /.docx present models of a checker with interfaces and addresses the
> following ISSUES
> 1. interfaces with or without clocking blocks
> a. Impact of using clocking blocks in interfaces? issues?
> 2. Checkers may be used as monitors or as drivers
> a. Interpretation of directions of modports
> i. As drivers, do we need a separate modport dedicated to the checker?
> ii. Can we reuse a modport defined for a DUT, but having a reverse
> interpretation of the port directions than those for the DUT?
> 3. Use of tasks defined in interfaces
> The SystemVerilog models are also provided.
>

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