[sv-ac] [SV-AC] Interfaces in checkers, Mantis 2751 // WIG

Attached is a fie that uses interfaces in a checker (I used a module to
perform the compilation / elaboration and simulations).
This model simulates OK.
This is Work In Progress. Below is a list of issues. I am looking for
feedback on your views and pitfalls of this approach
I used a clocking block in the interface, mainly because the clocking block
is very popular with methodologies like VMM and OVM.
1.1 Issues

1. Checkers may be used as monitors or as drivers

2. As drivers, do we need a separate modport dedicated to the checker,
or can we reuse a modport defined for a DUT, but having a reverse
interpretation of the port directions than those for the DUT?

3. What about tasks defined in checkers? Are there any issues in using
them, such as sampling, drivers?

4. What about parameterized interfaces? Allowed? Should or must the
values of the actual be the same as those applied to the DUT?

5. What is the impact of using clocking blocks in interfaces? issues?

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