[sv-ac] RE: Call to vote. Due August 16

From: Eduard Cerny <Eduard.Cerny@synopsys.com>
Date: Thu Aug 12 2010 - 13:17:08 PDT

SVDB 2412 ___Yes _X__No
http://www.eda-stds.org/mantis/view.php?id=2412
http://www.eda-stds.org/mantis/file_download.php?file_id=4450&type=bug

Unfortunately, I realized something a bit late:
The proposal does not say how this inference might interact with parameterized sequence used with .triggered when the default actual argument on a formal is $inferred_clock, and the sequence instance has no actual argument for that formal. I believe that there is no real problem, but it merits at least an example.

SVDB 2938 _X__Yes ___No
http://www.eda-stds.org/mantis/view.php?id=2938
http://www.eda-stds.org/mantis/file_download.php?file_id=4451&type=bug

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Received on Thu Aug 12 13:17:35 2010

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