Accellera SuperVerilog Assertion Activity: Re: [sv-ac] Call to v

From: ben cohen <hdlcohen@gmail.com>
Date: Mon Aug 02 2010 - 23:45:23 PDT

SVDB 1756 _X__Yes ___No

Vote to resolve as “No change required”

SVDB 2871 _X__Yes ___No

SVDB 2353 _ __Yes X__No

I need a discussion

Static variables declared in programs, interfaces, clocking blocks or
classes can also be accessed.

Are we saying this?

program x;
  logic a, b, clk;
  class c;
    logic w;
   endclass
  c c1=new();
  assert property(@ (posedge clk)
      c1.w |-> a);
endprogram

t.sv(8): c1.w |-> a);
** Error: t.sv(8): (vlog-2110) Illegal reference to class "c1".

On Sat, Jul 31, 2010 at 8:47 PM, Little Scott-B11206
<B11206@freescale.com>wrote:

>
>
> SVDB 1756 _X__Yes ___No
>
> http://www.eda-stds.org/mantis/view.php?id=1756
>
> Vote to resolve as “No change required”
>
>
>
> SVDB 2871 _X__Yes ___No
>
> http://www.eda-stds.org/mantis/view.php?id=2871
>
> http://www.eda-stds.org/mantis/file_download.php?file_id=4399&type=bug
>
>
>
> SVDB 2353 _X__Yes ___No
>
> http://www.eda-stds.org/mantis/view.php?id=2353
>
> http://www.eda-stds.org/mantis/file_download.php?file_id=4397&type=bug
>
>
>
> --
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Received on Mon Aug 2 23:46:11 2010

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Re: [sv-ac] Call to vote. Due August 2