[sv-ac] RE: Call to vote. Due July 26

SVDB 2938 ___Yes _X__No
http://www.eda-stds.org/mantis/view.php?id=2938
http://www.eda-stds.org/mantis/file_download.php?file_id=4406&type=bug

The two examples are quite different in nature.
The first one, even through the signal values are not consistent with the assertion result at the end of the time step, it is a correct and consistent interpretation, because this is conditional evaluation and the result is consistent with the condition at the end of the time step. I.e., the assertion should not fail. Or do I misinterpret the behavior? Do we really need this example?

Why using !b, might be simpler to use just b and change the values. The sentence "deferred assertions represent the final values of all signals before the Observed region, so they are important to keep in mind." should perhaps say "deferred assertion reporting is consistent with the final values of all signals before the Observed region, so they are important to keep in mind."

the second example is more the result of an evaluation artifact - short circuiting, and as indicated, it can be avoided by using |. This one is good.

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