[sv-ac] Minutes of SV-AC Meeting 7/13/2010

Minutes from SV-AC Committee Meeting
Date: 2010-07-13
Time: 16:00 UTC (9:00 PDT)
Duration: 1.5 hours

Agenda
------
- Reminder of IEEE patent policy.
See: http://standards.ieee.org/board/pat/pat-slideset.ppt

- Minutes approval

- Email ballot results

- Issue resolution/discussion

2732: Clarify timing diagram in Figure 16-4?Future value change
2398: Surprising (to some users) interaction between deferred assertions
        & short-circuiting
2491: Conflicting rules in 16.17 (D7)
2557: Rules for passing automatic variables to sequence subroutines are
        not clear
1756: The LRM does not indicate how the control tasks $asserton/off/kill
        affect verification statements in initial blocks
1763: The LRM does not define whether assertion control tasks affect
        sequence methods and events
2722: Errors in Figures 16-14, 16-15, and 16-16
2839: Contradictory statement of increment/decrement operators usage
1853: The proposal was already submitted by Brad Pierce, but apparently not
        voted on. The proposal is fine, and we should conduct an email vote.
2485: Submitted a proposal to fix the wording for immediate assertion types.
2558: Submitted a proposal to clarify the restrictions on automatic/dynamic
        variable references in a checker declaration

- Enhancement progress update

- Opens

Attendance Record:
------------------
         Legend:
                 x = attended
                 - = missed
                 r = represented
                 . = not yet a member
                 v = valid voter (2 out of last 3 or 3/4 overall)
                 n = not a valid voter
                 t = chair eligible to vote only to make or break a tie

Attendance re-initialized on 2010-07-06:

  v[xx] Laurence Bisht (Intel)
  v[x-] Eduard Cerny (Synopsys)
  v[xx] Ben Cohen
  v[xx] Surrendra Dudani (Synopsys)
  v[xx] Dana Fisman (Synopsys)
  v[xx] John Havlicek (Freescale)
  v[xx] Tapan Kapoor (Cadence)
  t[xx] Dmitry Korchemny (Intel ¿ Chair)
  v[xx] Scott Little (Freescale)
  v[xx] Manisha Kulshrestha (Mentor Graphics)
  v[xx] Anupam Prabhakar (Mentor Graphics)
  v[xx] Erik Seligman (Intel)
  v[x.] Samick Sengupta (Synopsys)
  v[xx] Tom Thatcher (Sun Microsystems ¿ Co-Chair)
    |- attendance on 2010-07-13
  |--- voting eligibility on 2010-07-13

Minutes
---------

1. Minutes from last meeting:
     Eric: Move to approve minutes
     Ben; Second
     Voting results: 13y, 0n, 0a

2. E-mail Ballot results -- Dmitry
    1627 Unanimous approval
    Some question over proper font for variable names in text, but will
leave
    it to editor
    John suggested to send to sv-bc for review.
    Dmitry will send it.

3. Issue resolution/discussion

Issue with variables (e-mail thread)
        Dmitry: Issue reported was that variable names used in assertions
                before declaration behaved differently. Rather than create
                an implicit declaration of the variable, the simulators
                seem to resolve the signal names at elaboration time, just
                like the variable was a cross-module reference.
        Ben: Variable should obey scoping rules
        Ed: Don't want to change the way it works now.
                This was how we intended it to work, although it wasn't
                written into the LRM.
        Dmitry: Some people may `include a file with assertions, but
            assertions may reference variables not declared yet
        Ed: Even if we wanted to change it, it would affect
        Ben: Should we add to LRM
        Ed: yes
        Manisha: even immediate assertions?
        Ben: Doesn't immediate assertion have to be in a process
        Ed: Immediate assertions are different.

        Dmitry: Checkers?
        Ben: Should it follow module instantations?
        Ed: Should follow assertion rules

        Dmitry: May have to ask Working Group for permission to work on this.
        Manisha: What about procedural concurrent assertions?
                Require declaration before use?
        Dmitry: I think yes.

2557
        Eric: One sentence Change.
        John: Would like to think about this more; perhaps an e-mail vote
        John: Three points in time: observed region, where match occurs,
                reactive region where subroutine executes, and
                Does automatic variable exist at the match time?
        Dmitry: Will call for an e-mail vote

2732 Dmitry: Postpone to next meeting
2938
        Eric: Short-circuiting
        Eric: Is this documented?
            When you hit flush point: we don't report attemts so far
        John: Does proposal change anything
        Eric: Not suggesting changing anything
        Dmitry: Will defer to next meeting,
2491
        Eric: Not sure of the problem:
                Has sent e-mail to Doron
        John: doesn't think there is a problem.
                We're not being careful about sequence declaration, vs
                instance.
                Rule e doesn't exclude instances
                Rule f specifies case where you have to have an instance
        Ed: Is "maximal property" defined
                Is solutionjust to define the term?
                What does "maximal property" mean?
        John: Thinks that maximal property meant the largest expression you
                could get using the property grammar. That doesn't include
                disable iff, but does include the clocking statement.
        Eric: John will write opinion as a note on the Mantis item.
                Should we open separate Mantis to define "Maximal property"
        Ed: Do we really need rule F
        John: Maybe it doesn't need to be a normative restriction
        Ed: Rule e subsumes f
        John: Rule f points out one consequence of Rule e

4. Enhancements progress update
        Real Types
        Checker output arg
        Interfaces & checkers
        Assertion system functions

     Interfaces & checkers
        Ben: Wrote a use model
        Ben: Question: Should checkers be able to drive interface inputs
        Dmitry: Yes
        Ed: Sometimes checker could be used as constraint.

        Ben: OVM, VMM typically use classes tied to virtual interface.
            But you can't have checker in class. so why is this needed?
            Still unclear on use model.

        Ben: Original thought was just to allow a better connection to a
            checker.
        Tom: Don't necessarily need to drive interface inputs for formal.
            Instead, an assume property would constrain the value of the
            input.

     Assertion system function
        Eric: Concentrating on errata now.

     Clock inferenceing & sequence
        Anupam: Have a good idea of what to propose.

     Real types
        Scott: Concentrating on errata.

     Checker output arguments
        Lawrence has documented use cases

Next meeting: Next week.

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