Re: [sv-ac] Proposal uploaded for Mantis 2722

Minor changes:
$rose(data_phase) |-> ##[1:5] ((irdy==0) && ($fell(trdy) || $fell(stop))) ;
  // OK
*<Then, at clock tick 6, property*
*data_end is evaluates to true because stop gets asserted while irdy is
asserted.> *
Should be:
Then, at clock tick 6, property
data_end is evaluates to true because $fell(stop) evaluates to true while
irdy==0 is asserted.

On Fri, Jul 9, 2010 at 4:56 PM, Thomas J Thatcher <
thomas.thatcher@oracle.com> wrote:

> Hello Everyone,
>
> I have uploaded a proposal for Mantis 2722. Nothing controversial, but
> probably a few details to fix. We can discuss it at the next meeting.
>
> Thanks,
>
> Tom
>
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