RE: [sv-ac] automatic variiables in clock expr // virtual interface

You ment that
 always @vi.clk $display("event" ,$time); //legal???
Is not sensitivy list - becouse it is : "the statements within an always
block are procedural"

I think that this definition suffers from lack of explicit definition what
is sensitivity list.
This term is widely used in LRM but never defined.
I believe that there is a mantis item for lack of sensitivity list
definition

DANiel

-----Original Message-----
From: Rich, Dave [mailto:Dave_Rich@mentor.com]
Sent: Tuesday, June 15, 2010 8:34 AM
To: neil.korpusik@oracle.com; sv-ac@server.eda.org
Cc: danielm
Subject: RE: [sv-ac] automatic variiables in clock expr // virtual interface

Daniel,

I believe the intent of the rule was: These components *shall* only be used
in procedural statements. period.

A continuous assignment is not a procedural statement; the statements within
an always block are procedural.

The rule was mainly to avoid null virtual interface references at start-up
time, as well as performance penalties for having dynamic sensitivity lists.

Dave

> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
Neil
> Korpusik
> Sent: Monday, June 14, 2010 5:30 PM
> To: sv-ac@server.eda.org
> Cc: danielm
> Subject: RE: [sv-ac] automatic variiables in clock expr // virtual
> interface
>
> <forwarding email from Daniel Mlynek>
>
> -------- Original Message --------
> From: "Daniel Mlynek" <danielm@aldec.com>
> To: "'Bresticker, Shalom'" <shalom.bresticker@intel.com>,
> <ben@systemverilog.us>, <sv-ac@eda.org>
> Subject: RE: [sv-ac] automatic variiables in clock expr // virtual
> interface
> Date: Mon, 14 Jun 2010 15:42:05 +0200
>
>
> Sensitivity list is also illegal. Could someone give an example for
> illegal usage of virtual interface on sensitivity list, I see nothing
> wrong in
> example:
>
> interface ifc;
> logic [7:0] data;
> bit clk;
> initial $monitor (data);
> initial forever #5 clk =~ clk;
> endinterface
>
> module test;
> ifc Rx();
> virtual ifc vi=Rx ;
> byte data1;
> initial forever #5 data1++;
> //assign vi.data=data1; //illegal - ok
> always @vi.clk $display("event" ,$time); //legal???
> initial #101 $finish;
> endmodule
>
>
> DANiel
>
> _____
>
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
> Bresticker, Shalom
> Sent: Monday, June 14, 2010 3:25 PM
> To: ben@systemverilog.us; sv-ac@eda.org
> Subject: RE: [sv-ac] automatic variiables in clock expr // virtual
> interface
>
>
> Maybe the following (25.9):
>
> Once a virtual interface has been initialized, all the components of
the
> underlying interface instance are directly available to the virtual
> interface via the dot notation. These components can only be used in
> procedural statements; they cannot be used in continuous assignments
or
> sensitivity lists.
>
> Shalom
>
>
>
> _____
>
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
ben
> cohen
> Sent: Monday, June 14, 2010 4:17 PM
> To: sv-ac@eda.org
> Subject: [sv-ac] automatic variiables in clock expr // virtual
interface
>
>
> See http://verificationguild.com/modules.php?name=Forums
>
<http://verificationguild.com/modules.php?name=Forums&file=viewtopic&p=1
8
> 142
> #18142> &file=viewtopic&p=18142#18142
> Lrm reference ?
> Question is somewhat related to our upcoming discussion in interfaces
and
> checkers.
> Ben
>
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