RE: [sv-ac] 2804 proposal uploaded

Hi Erik,
 
My main concern with this is that in case of hierarchical references
(e.g. always @(top.cb)), the incremental flow will not be able to infer
clocks at compile time. In this case the cb could be a clocking block,
event or just a variable. Since rule (2) eliminates any possibility of
inferring 'reset' as the clock, why do we need an edge for inferring
clock ? Also, when user writes the clock explicitly for an assertion,
there is no such rule about having an 'edge'. Without, edge specifier,
it means any edge in Verilog.
 
Thanks.
Manisha
 
 

________________________________

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
Seligman, Erik
Sent: Wednesday, June 02, 2010 3:33 AM
To: Korchemny, Dmitry; sv-ac@server.eda.org
Subject: [sv-ac] 2804 proposal uploaded

Hi guys-I have uploaded a new proposal at
http://www.verilog.org/mantis/view.php?id=2804, which I think captures
the results of this morning's discussion. Please take a look & comment
if further changes are needed.

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