[sv-ac] RE: Uploaded proposal for Mantis 0002804

I think to define this further, we need to answer these questions:

- Is it acceptable to require tools to dive down into any instantiated task or clocking block and fully analyze the contents to determine how to infer the clock? (What are the implications for partial/separate compilation?)

- Or does it make more sense to define the rules in such a way that they only need to examine the locally visible contents or the procedure?

Perhaps we can discuss these today.

From: Korchemny, Dmitry
Sent: Tuesday, June 01, 2010 5:32 AM
To: Surrendra Dudani; Seligman, Erik; sv-ac@eda.org
Subject: RE: Uploaded proposal for Mantis 0002804

I agree. Also when clk is defined as a checker formal corresponding to posedge/negedge/edge clk.

Dmitry

From: Surrendra Dudani [mailto:Surrendra.Dudani@synopsys.com]
Sent: Tuesday, June 01, 2010 3:30 PM
To: Korchemny, Dmitry; Seligman, Erik; sv-ac@eda.org
Subject: RE: Uploaded proposal for Mantis 0002804

One more item we need to clarify regarding the inference of clocks. What if the a clocking block event is used in the always block, where the event expression of the clocking block complies with the inference rules? I think the LRM is silent about the use of clocking block events. For example,

clocking cb @(posedge clk); endclocking
 always @(cb) begin
  assert property(a);
end

Surrendra
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Korchemny, Dmitry
Sent: Sunday, May 30, 2010 11:55 AM
To: Seligman, Erik; sv-ac@eda.org
Subject: [sv-ac] RE: Uploaded proposal for Mantis 0002804

Hi Erik,

We need allow a case when a system task is called in the procedure, e.g., inferring the clock in the following example should be legal:

always @(posedge clk) begin
  assert property(a);
 $display ("%b", clk);
end

A problem, however, remains, since a normal task may wrap a system task:

task my_display(logic sig);
  $display ("%b", clk);
endtask

always @(posedge clk) begin
  assert property(a);
 my_display (clk);
end

Thanks,
Dmitry

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Seligman, Erik
Sent: Friday, May 14, 2010 7:26 PM
To: sv-ac@eda.org
Subject: [sv-ac] Uploaded proposal for Mantis 0002804

Hi guys-I uploaded a proposal for this item related to inferring clocks for procedural concurrent assertions, at http://www.verilog.org/mantis/view.php?id=2804 . Please take a look & send comments.

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