Re: [sv-ac] RE: proposal for 2732

Hi John,
  Agreed, this is what I meant by WA. I've seen a few as:

1. Overloading $error - works in 1 tool as I am told

2. Use SV-C-SVTB as you suggested

3. Use SV-API (assertion API)

4. atleast 1 EDA vendor claims to do this internally/automatically

5. Force users to use action blocks.

My real point is to make it easiest for users without too much pain,
extra code etc.

Thanks
Srini
www.cvcblr.com

On 5/27/10, John Michael Williams <john@svtii.com> wrote:
> Hi Srini.
>
> In verilog, a count could be implemented by using a
> timing-check notifier.
>
> Perhaps a predefined class method could be implemented
> to toggle a reg and thus tie the C++ to the Verilog sides
> of SV?
>
> On 05/26/2010 10:24 PM, Srinivasan Venkataramanan wrote:
>> Hello all,
>> Somewhat related enhancement - is there now a simple mechanism to
>> communicate SVA errors back to a class based SV-TB env (say VMM/OVM/UVM
>> etc.)? This has been a real pain for users and a unified language must
>> provide it inside the language itself. Sure there are work-arounds, but I
>> sincerely believe this is needed in the language. At the minimum can we
>> have
>> an error-count to indicate that a SVA error has occurred during the
>> simulation so that in a final block or so one can use it to flag the test
>> as
>> PASS/FAIL?
>>
>> Sorry if this has already been discussed another Mantis - kindly point me
>> to
>> the same.
>>
>> Thanks
>> Srini
>> www.cvcblr.com
>>
>
> --
> John Michael Williams
> Senior Adjunct Faculty
> Silicon Valley Technical Institute
>
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