[sv-ac] vhdl and SystemVerilog tie in

The IEEE 1800-2009 LRM has no mention of VHDL tie in or link into
SystemVerilog.
Vendors have adopted the "bind", but that is not in the LRM for binding VHDL
modules into SystemVerilog.
This sv-ac is probably the wrong forum to address this, but many users see
the need for such a feature.
I believe that it should be addressed somewhere in the IEEE 1800.
Below is an example of such an issue.
Accessing Constants in VHDL Packages in
SystemVerilog<http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=3890>
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=3890

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