RE: [sv-ac] Q: fix for rule (b) in 16.15.6 to allow inferred clock when expression appears in procedural assertion

I believe the intent was to emulate normal synthesizable RTL semantics for flip flops and distinguish the clock from the reset. That is, the basic synthesizable flip flop form is roughly:

always @(posedge clk or posedge rst)
        if (rst)
                out <= 0;
        else
                out <= in;

That is, the event control contains the clock and the asynchronous reset. One of the distinctions between the clock and the reset is that the clock does not appear inside the procedure body whereas the reset does.

(One might want to consider other non-design logic statements in which the clock could legitimately appear, such as in a $display statement.)

> But perhaps I'm missing some reasoning here. Does anyone
> remember the motivation for the original rule? Was it due to
> difficulties implementing tools that could handle this, or
> some insight into the usual intent of such code?

Regards,
Shalom
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