[sv-ac] sv[ac]: checker // if blocking timing and default clock then legal?

Question:
LRM 16.15.6 (see below) states that the clock from an always cannot be
inferred into an assertion.
What if I have a default clocking ?
What if I use a checker?
Thus, is the following legal?

*checker *chk_test(logic a, clk);
   *default clocking* default_clk @ (*posedge *clk); *endclocking*
    ap_a: a*ssert property*(a);
 *endchecker *: chk_test

*checker *chk_test_better(logic a, clk);
    ap_a: a*ssert property*(@ (posedge clk) a); *// DO I NEED TO BE EXPLICIT
ON THE clocking event ?? *
 *endchecker *: chk_test_better

*module *m(logic x, clk);
  *logic *v, c, w, y;
*always *@(*posedge *clk) *begin*
  v=1;
  *if*(w) chk_test chk_test_c(c, clk); // checker instantiation // LEGAL?
  *if(*y) chk_test chk_test_v(v, clk);  // or ILLEGAL because of no clock ?
*end*
*endmodule : m*

LRM 16.15.6 Embedding concurrent assertions in procedural code
A clock shall be inferred for the context of an always or initial procedure
that satisfies the following requirements:
1) There is no blocking timing control in the procedure.
2) There is exactly one event control in the procedure.

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