[sv-ac] Can checker assign value to variable outside its boundary?

17.7.1 states "It shall be illegal to reference a checker variable using its
hierarchical name in assignments"
(Note: that means that a module cannot access a checker's variable)  That is
not my question.
17.2 states "Variables used in a checker that are neither formal arguments
to the checker nor internal variables of the
checker are resolved according to the scoping rules from the scope in which
the checker is declared."
However, *nowhere in the LRM does it state that a checker cannot assign a
value to a variable in the checker's boundary. *
*Thus, by omission, it is legal to assign a value to a variable outside the
checker's boundary.  *
Maybe it's a misconception on my part, *but all ports of a checker are
inputs.  The obvious intent in making ports inputs is prevent the assignment
to objects outside the checker boundary.  *In a way, allowing such
assignments defeats the requirement that ports must be inputs.
*Question*: *Can a checker assign a value to a variable in it's scope
declaration?  *
Below is an example of my understanding.  However, LRM is unclear on this.
*module *test;
  logic *a*, b, c. clk;
   task t;
      logic t1;
      t1<= 1'b1;
      a <= t1;
    endtask

  some_other_module *m_other*;  *// has local variable z*

  checker c(logic clk);
    logic x, y;
     always (@ (posedge clk)  begin
       * a <= 1'b0;  // ILLEGAL ??   Can write to outside checker boundary?
*
*       t.t1 <= 1'b1;  ILLEGAL  ?? *
      x <= 1'b1; // OK
      y <= b;  // OK, can read b
     *m_other.z <= 1'b1;  // ILLEGAL* ??
    end
endchecker : c
Ben Cohen

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