Hi,
In SV 2009 draft 7a LRM, it is mentioned:
16.6.3 Operators
All operators that are valid for the types
described in 16.6.1 are allowed with the exception of assignment
operators and increment and decrement operators. SystemVerilog includes
the C assignment operators, such as +=, and the C increment and
decrement operators, ++ and --. These operators cannot be used in
expressions that appear in assertions. This restriction prevents side
effects.
However, BNF of sequence_match_item shows following rules:
sequence_match_item ::=
operator_assignment
| inc_or_dec_expression
| subroutine_call
Are they not contradictory?
--
Regards
Surya
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Received on Wed Aug 5 21:44:41 2009