RE: [sv-ac] rules for concurrent assertion clock in procedural code

> In the example being discussed:
> 
> default clocking dclk @(posedge clk);endclocking 
> always @(negedge clk) begin
>   as1: assert property (a ##1 a);
>   as2: assert property (@(posedge clk_s) clk && sig); 
> end 
> 
> the standard as currently written, says that no clock can be 
> inferred from the procedural block, so default clocking applies.  If
> this is not what the user wants, then they need to be explicit. 

I'm sorry, as a user I strongly disagree.  The subtlety of 
implied clocks is already a potential source of great 
confusion; this is only adding to it.  I suggest that any
typical user would regard the assertions as purely passive,
having no effect on the flow of execution of the always-
procedure, and therefore would expect as1 to be clocked 
by (negedge clk).  Having the clock lapse back to the
default clocking is a subtle error that might not surface
until far too late.  Excluding use within assertions
from the clock inference rules is easy and intuitive.
-- 
Jonathan Bromley



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