RE: [sv-ac] rules for concurrent assertion clock in procedural code

> it looks to me like we need a Mantis on 
> this, explicitly excluding concurrent assertion
> clock events from rule b. 

Surely the problem here is that you're trying to define,
in the LRM, the way in which synthesis infers a clock
from a particular kind of always-procedure coding style?

> Anyone know if this is already documented anywhere?

You *may* be able to appeal to IEEE 1364.1 (synthesis subset)
standard.  I'm not an expert on that standard - I don't
even possess a copy! - so can't comment on the details.
But it certainly defines various ways to infer a clock
from an always-procedure.

As someone already mentioned, any "passive" use of the
clock (such as in a $display) must not affect clock 
inference.  Presumably the same applies to any use 
of the clock in assertions.  What about other debugging
code, which may perhaps be enclosed in synthesis_off/on
directives?  For example, the generation of a delayed
version of the clock for some sampling required for
debug?  I fear that you'll have a tough time getting
this right unless you put into the LRM a bunch of things
that have traditionally been regarded as de-facto 
synthesis territory.

The restriction about "no term appears elsewhere" is essential
to deal with the usual asynchronous-reset coding style:

  always @(posedge clock or posedge asyncReset)
    if (asyncReset)
      Q <= 0;
    else
      Q <= D;
In this case, asyncReset clearly is not a clock.
It *is* a reset, though, and one might reasonably
hope for it to be inferred as an asynch disable for
assertions added to the block....
-- 
Jonathan Bromley
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