[sv-ac] P1800-2009: checker formal arguments may not be connected to interfaces // WHY?

pg 415 "Unlike modules, interfaces, and programs, checker formal arguments
may not be connected to interfaces."[Ben] Why this restriction?  The
interface is one of the beauty of SystemVerilog.  Are we saying that the
following is illegal?
interface fifo_if(..);  modport fslave_if_mp (..); .. endinterface : fifo_if
checker fifo_chker (logic clk, fifo_if.fslave_if_mp f_if, ...);
   property p_t1_full;  @ (posedge clk)
      property p_push_error;
       @ (posedge clk)
         not (f_if.push && f_if.full && f_if.pop);
      endproperty : p_push_error
     ap_push_error : assert property (p_push_error);
endchecker
If the rationale is that interfaces can have outputs, then we can restrict
the usage in that in checkers, we cannot assign to a port, which is the case
anyways.
Without the access to interfaces in formal arguments, we lose a lot.  That
would mean that every element of the interface would have to be added to the
port list, unless we want to use hierarchical references. Thus, if an
interface with 100 signals, instead of passing that interface as a name, one
would have to enter 100 elements in the formal arguments of the checker!
 That defeats the use of interfaces!!!!
Before I put that in a Mantis, I would like to hear some feedback on this
issue.  Why the restriction? wouldn't it be better to include the interface
in formal arguments of a checker?
Thanks,
Ben Cohen

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