RE: [sv-ac] Proposal uploaded for Mantis 2656 (Ballot Comment #84)

Hi Tom,

Maybe we can explain this without distinguishing between simulation and formal verification:

The global clock behaves just as any other clocking event with an additional significance, that it is
considered to be the primary system clock (see F.5.1 ).
...
This assertion is equivalent
to
assert property(@clk a);
with additional indication that clk is the primary system clock

What do you think?

Dmitry

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On Behalf Of ben cohen
Sent: Wednesday, April 22, 2009 9:27 PM
To: Thomas.Thatcher@sun.com
Cc: sv-ac@server.eda.org
Subject: Re: [sv-ac] Proposal uploaded for Mantis 2656 (Ballot Comment #84)

Looks good to me.
Ben
On Wed, Apr 22, 2009 at 11:16 AM, Thomas Thatcher <Thomas.Thatcher@sun.com<mailto:Thomas.Thatcher@sun.com>> wrote:
Hello Everyone,

I have uploaded a proposal for Mantis 2656 (Ballot Comment #84).

This change, although simple, might generate some controversy!

The original comment suggested that the simple example, which illustrates a reference to a global clocking event be replaced by one which better illustrates the differences between formal verification and simulation.  However, this paragraph is just an overview paragraph, and I did not think this was the place to go into details.  So I made a few changes to the paragraph which downplay the differences between formal verification and simulation and highlight their common behavior.

Comments welcome!

Tom

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