RE: [sv-ac] P1800-2009: checker: Is "assign" legal in checkers?

See

   http://www.eda-twiki.org/cgi-bin/view.cgi/P1800/SvScMeetingMinutes200805F2F

-- Brad

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of ben cohen
Sent: Friday, March 27, 2009 9:54 AM
To: sv-ac@eda.org
Subject: [sv-ac] P1800-2009: checker: Is "assign" legal in checkers?

LRM seems to indicate that this is illegal, but are some vendors allowing this?
Any reason as to why it is illegal?
checker c(logic b, d, e, f, clk);
  logic a;
  assign a = b && d;  // Legal?
// 17.1 LRM:   The modeling mechanism in checkers is limited to nonblocking assignments only
   assert property (@ (posedge clk) a |=> e);
endchecker : c
// Ben

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