RE: [sv-ac] Special assert syntax

From: Kulshrestha, Manisha <Manisha_Kulshrestha_at_.....>
Date: Mon Mar 09 2009 - 01:59:28 PDT
Hello Surya,

The syntax you have mentioned is not in the standard. But the standard has an equivalent feature called 'deffered assertions'. They are described in 16.4. I am not aware about the exact differences but deferred assertions were based on assert final concept.

Manisha

-----Original Message-----
From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On Behalf Of Surya Pratik Saha
Sent: Monday, March 09, 2009 1:22 PM
To: sv-ac@server.eda.org
Subject: [sv-ac] Special assert syntax

Hi,
Recently I came across one particular assert syntax which supported by a 
standard simulator. This SVA feature involves so called "final assertions".
which have a form such as:

assert final (a) else $error ("Failed");

It appears that assertions of this type would be acceptable inside and 
outside procedural
code.

Though I did not see any such enhancements in SV 2009 draft LRM. Can 
anybody let me know the details about this syntax.

-- 
Regards
Surya




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Received on Mon Mar 9 02:01:45 2009

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