RE: [sv-ac] Meaning of automatic variable reference in sequence match item

Hi Surya,

Here is an example:

always @(posedge clk) begin
                automatic logic a;
                …
                assert property((x, sub(a)) |-> y);
end

However, there are several problems in the text itself that should be addressed:

evaluate the sequence match. The variable passed by value as an input shall be of a type allowed in 16.6.1.
An automatic variable shall not be passed as an argument to a subroutine call either as input or ref type. An
automatic variable may be used as a constant input for a subroutine call from an assertion statement in procedural
code (see 16.15.5).

It is not clear how to reconcile the fact that the automatic variable cannot be passed to a subroutine with the fact that it may be used as a constant input. I think that the sentence you pointed out:

An automatic variable shall not be passed as an argument to a subroutine call either as input or ref type.

should be deleted. Also the reference 16.15.5 is wrong, and should be 16.15.6 Embedding concurrent assertions in procedural code. I filed a new Mantis item 2557 about it.

Dmitry

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On Behalf Of Surya Pratik Saha
Sent: Monday, January 05, 2009 6:24 AM
To: sv-ac@server.eda.org
Subject: [sv-ac] Meaning of automatic variable reference in sequence match item

Hi,
I did get any reply of this mail sent some days back. So I am resending it.

In SV 2009 draft LRM, it is mentioned:
An automatic variable shall not be passed as an argument to a subroutine call either as input or ref type.

How an automatic variable can be referenced inside sequence match item, which is actually enclosed inside a sequence declaration. And sequence declaration does not allow automatic variable declaration like task/function etc. Please give some e.g. if I am wrong.


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Regards

Surya

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