Hi Doron, Thanks for the clarification. But I am not clear about an 'empty match' as LRM mentioned: "It shall be an error for an instance of a named sequence with an inout or output local variable formal argument to admit an empty match." Can you please give us an exampled regarding this. Regards Surya -------- Original Message -------- Subject: Re:[sv-ac] What is the meaning of 'match' here? From: Bustan, Doron <doron.bustan@intel.com> To: Surya Pratik Saha <spsaha@cal.interrasystems.com>, sv-ac@server.eda.org <sv-ac@eda.org> Date: Wednesday, December 24, 2008 1:06:56 PM > Hi Surya, > > At 16.7 it says "The sequence feature provides the capability > to build and manipulate sequential behaviors. The simplest sequential behaviors are linear. A linear > sequence is a finite list of SystemVerilog boolean expressions in a linear order of increasing time. The linear > sequence is said to match along a finite interval of consecutive clock ticks provided the first boolean expression > evaluates to true at the first clock tick, the second boolean expression evaluates to true at the second > clock tick, and so forth, up to and including the last boolean expression evaluating to true at the last clock > tick. A single boolean expression is an example of a simple linear sequence, and it matches at a single clock > tick provided the boolean expression evaluates to true at that clock tick. > More complex sequential behaviors are described by SystemVerilog sequences. A sequence is a regular > expression over the SystemVerilog boolean expressions that concisely specifies a set of zero, finitely many, > or infinitely many linear sequences. If at least one of the linear sequences from this set matches along a finite > interval of consecutive clock ticks, then the sequence is said to match along that interval." > > An example of an erroneous match is: > > sequence S(local output bit v); > (a[->1], v = 1) > or > (b[->1]); > endsequence > > in any interval of a computation where "b" appears before "a", there is a match of S to the interval, but the value of "v" is undefined. This is considered an error. > > > > >>> -----Original Message----- >>> From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On >>> Behalf Of Surya Pratik Saha >>> Sent: Wednesday, December 24, 2008 7:55 AM >>> To: sv-ac@server.eda.org >>> Subject: [sv-ac] What is the meaning of 'match' here? >>> >>> Hi, >>> As per 2009 SV draft LRM: >>> "It shall be an error if there exists a match of the named >>> sequence for which an inout or output local variable formal argument is >>> unassigned at the completion >>> of the match. At the completion of a match of the instance of the named >>> sequence, the value of >>> the inout or output local variable formal argument shall be cast to the >>> type of and assigned to the >>> local variable whose reference is the associated actual argument." >>> >>> What is the meaning of 'match' here. One example snippet will be better. >>> >>> -- >>> Regards >>> Surya >>> >>> >>> >>> >>> -- >>> This message has been scanned for viruses and >>> dangerous content by MailScanner, and is >>> believed to be clean. >>> >>> >>> -- >>> This email was Anti Virus checked by Astaro Security Gateway. >>> http://www.astaro.com >>> > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > > > > > > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Dec 23 23:52:48 2008
This archive was generated by hypermail 2.1.8 : Tue Dec 23 2008 - 23:52:58 PST