RE: [sv-ac] ensure vs. verify

From: Korchemny, Dmitry <dmitry.korchemny_at_.....>
Date: Sun Dec 07 2008 - 22:44:43 PST
Hi Lisa,

Yes, "flag" sounds better than "verify" to me.

Thanks,
Dmitry

From: Lisa Piper [mailto:ljpiper619@aol.com]
Sent: Sunday, December 07, 2008 5:54 PM
To: Korchemny, Dmitry; sv-ac@server.eda.org; stuart@sutherland-hdl.com; Neil.Korpusik@sun.com
Subject: RE: [sv-ac] ensure vs. verify

Dmitry,

Can we use the word "flag" or "report":

In addition, assertions can be used to provide functional coverage and to ensure verify that flag when input
stimulus that is used for validation does not conform conforms  to assumed requirements.


________________________________
From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On Behalf Of Korchemny, Dmitry
Sent: Sunday, December 07, 2008 10:03 AM
To: sv-ac@server.eda.org; stuart@sutherland-hdl.com; Neil.Korpusik@sun.com
Subject: [sv-ac] ensure vs. verify

Hi all,

Following IEEE requirements the editor has changed "ensure" and "guarantee" with other words. One such example is the beginning of 16.2:

An assertion specifies a behavior of the system. Assertions are primarily used to validate the behavior of a
design. In addition, assertions can be used to provide functional coverage and to ensure verify that input
stimulus that is used for validation conforms to assumed requirements.

IMO "ensure" is much better suited here than "verify", since in formal verification the assumptions normally cannot be verified unless you consider them in a larger context. Therefore I am curious whether better suggestions are available.

Neil, is it compulsory to change the world "ensure" in this case? If not, I would prefer to keep it unchanged.

Thanks,
Dmitry

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Received on Sun Dec 7 22:47:35 2008

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