[sv-ac] ensure vs. verify

From: Korchemny, Dmitry <dmitry.korchemny_at_.....>
Date: Sun Dec 07 2008 - 07:03:15 PST
Hi all,

Following IEEE requirements the editor has changed "ensure" and "guarantee" with other words. One such example is the beginning of 16.2:

An assertion specifies a behavior of the system. Assertions are primarily used to validate the behavior of a
design. In addition, assertions can be used to provide functional coverage and to ensure verify that input
stimulus that is used for validation conforms to assumed requirements.

IMO "ensure" is much better suited here than "verify", since in formal verification the assumptions normally cannot be verified unless you consider them in a larger context. Therefore I am curious whether better suggestions are available.

Neil, is it compulsory to change the world "ensure" in this case? If not, I would prefer to keep it unchanged.

Thanks,
Dmitry
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.
Received on Sun Dec 7 07:04:23 2008

This archive was generated by hypermail 2.1.8 : Sun Dec 07 2008 - 07:04:33 PST