RE: [sv-ac] 16.4 questions

Hi Shalom,

 

John will open a new Mantis item to address your first three questions.
Meanwhile we asked Stu to replace Clause 4 with Clause 14 (this should
be more relevant. As for the last question is concerned we asked Stu to
replace "simulation ticks" with "simulation time steps"

 

Thanks,

Dmitry

 

________________________________

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Bresticker, Shalom
Sent: Tuesday, May 06, 2008 12:42 PM
To: sv-ac@server.eda.org
Subject: [sv-ac] 16.4 questions

 

Hi, 

I have a couple of questions about 16.4 in Draft 5. Since the editor has
not yet implemented the SV-AC Manti, I realize the questions might not
still be relevant.

Para. 2 says, 

The values of variables used in assertions are sampled in the Preponed
region of a time slot, and the assertions 
are evaluated during the Observed region. If a variable used in an
assertion is a clocking 
block input variable, the variable shall be sampled by the clocking
block with #1step sampling. 
Any other type of sampling for the clocking block variable shall result
in an error. The assertion using the 
clocking block variable shall not do its own sampling on the variable,
but rather use the sampled value 
produced by the clocking block. This is explained in Clause 4. 

1. The first reference to a clocking block variable is to an input
variable. Should that include inouts? 

2. The following references to clocking block variables do not specify
'input'. Is that to be understood? 

3. The last sentence references Clause 4. I don't understand what is
intended. Clause 4 does not mention assertions or clocking blocks.

4. The term "simulation tick" is used in the LRM only with respect to
Figure 16-1 and 16-3 and is thus undefined. It would be better to use a
term consistent with the rest to the LRM. I think "time step" is the LRM
term for "tick".

Thanks, 
Shalom 

Shalom Bresticker 
Intel Jerusalem LAD DA 
+972 2 589-6582 
+972 54 721-1033 

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