RE: [sv-ac] Review of Draft5 - 16.9 till end of chapter

I also reviewed these sections, and agree with Yaniv's assessment.

________________________________

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Fais Yaniv
Sent: Tuesday, May 06, 2008 11:50 PM
To: sv-ac@server.eda.org
Subject: [sv-ac] Review of Draft5 - 16.9 till end of chapter



Hi all,

 

I have reviewed chapter 16, from 16.9 till the end of the chapter and I
found the following issues:

* 16.14.7 - "iff" was replaced with "if" , should be "if and only if"

* In the following paragraph (16.9 , page 336) the editor replaced
"must" with "shall" like in many other places , I'm not sure this is
correct in this case since "must" here was not used to define a
requirement of tool implementation or from the user but a fact which is
resulting from the previous sentences , John has suggested rewriting the
last sentence as: "Such a variable is dynamically created when needed".

 

The use of a static SystemVerilog variable implies that only one copy
exists. If data values need to be checked in pipelined designs, then for
each quantum of data entering the pipeline, a separate variable can be
used to store the predicted output of the pipeline for later comparison
when the result actually exits the pipe.

This storage can be built by using an array of variables arranged in a
shift register to mimic the data propagating through the pipeline.
However, in more complex situations where the latency of the pipe is
variable and out of order, this construction could become very complex
and error prone. Therefore, variables are needed that are local to and
are used within a particular transaction check that can span an
arbitrary interval of time and can overlap with other transaction
checks. Such a variable must shall thus be dynamically created when
needed within an instance of a sequence and removed when the end of the
sequence is reached

 

Yaniv

 


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