[sv-ac] RE: [sv-sc] Re: ConcurrentAssertNewProposal

From: Korchemny, Dmitry <dmitry.korchemny_at_.....>
Date: Tue May 06 2008 - 05:39:21 PDT
I agree with Adam, the cases when a TB drives signals with a small delay
are very common. I think that having (clocked) concurrent assertions in
combinatorial always procedures is absolutely critical.

Thanks,
Dmitry

-----Original Message-----
From: owner-sv-sc@server.eda.org [mailto:owner-sv-sc@server.eda.org] On
Behalf Of Steven Sharp
Sent: Tuesday, May 06, 2008 1:00 AM
To: Seligman, Erik; adam.krolnik@verisilicon.com
Cc: gordonv@model.com; sv-sc@server.eda.org; sv-ac@server.eda.org
Subject: Re: [sv-sc] Re: ConcurrentAssertNewProposal


>From: Adam Krolnik <adam.krolnik@verisilicon.com>

>The signal 'ready_now' changes in a later timestep compared to the rest

>of the variables. We want to prevent
>false failures in logic like this as well. Prior evaluations of the 
>assertion need to be stopped and not reported
>as a failure.

Essentially, you want prior evaluations of the assertion to be stopped
unless they have been clocked once since being triggered.

Steven Sharp
sharp@cadence.com


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Received on Tue May 6 05:39:58 2008

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