RE: [sv-ac] assertion allowed variables

Should it be SV-AC item?

 

Dmitry

 

________________________________

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of danielm
Sent: Thursday, April 03, 2008 6:03 PM
To: Bresticker, Shalom; sv-ac@server.eda-stds.org
Subject: RE: [sv-ac] assertion allowed variables

 

so another mantis need to be filed.

 

BTW : Who can report a Mantis items for SV, I can report mantis for OVL
which is held inthe same data base - so can I raport also mantis for SV?

 

 

DANiel

 

________________________________

From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Thursday, April 03, 2008 1:34 PM
To: danielm; sv-ac@server.eda-stds.org
Subject: RE: [sv-ac] assertion allowed variables

Note that 13.4 in Draft 4 says,

"It shall be illegal to call a function with output, inout, or ref
arguments in an event expression, in an expression within a procedural
continuous assignment, or in an expression that is not within a
procedural statement. However, a const ref function argument shall be
legal in this context (see 13.5.2)."

16.5 has the paragraph you cite.

 

17.5.11 has, "Functions that appear in constraint expressions cannot
contain output or ref arguments (const ref are allowed)."

 

I agree that both these places should specify 'inout' as well.

 

Shalom

 

	
________________________________


	From: owner-sv-ac@server.eda.org
[mailto:owner-sv-ac@server.eda.org] On Behalf Of danielm
	Sent: Thursday, April 03, 2008 10:24 AM
	To: sv-ac@server.eda-stds.org
	Subject: RE: [sv-ac] assertion allowed variables

	ieee: 1800-2005 There is:

	Functions that appear in expressions cannot contain output or
ref arguments (const ref are allowed).

	it should be?

	Functions that appear in expressions cannot contain output,
inout or ref arguments (const ref are allowed).

	DANiel

	
	 

	
________________________________


	From: owner-sv-ac@server.eda.org
[mailto:owner-sv-ac@server.eda.org] On Behalf Of danielm
	Sent: Thursday, April 03, 2008 9:04 AM
	To: 'Seligman, Erik'
	Cc: sv-ac@server.eda-stds.org
	Subject: RE: [sv-ac] assertion allowed variables

	AFAIK to get the 2008 draft i have to pay for it, or  company
have to donate accellera - it is still not clear for me.

	The pdf is protected with password so unfortunatelly I cannot
check it .

	 

	 

	DANiel

	 

	
________________________________


	From: Seligman, Erik [mailto:erik.seligman@intel.com] 
	Sent: Wednesday, April 02, 2008 4:11 PM
	To: danielm
	Subject: RE: [sv-ac] assertion allowed variables

	Hi Daniel-- 

	Have you checked the correspondng section of 2008 draft 4?

	 

	 

	
________________________________


	From: owner-sv-ac@server.eda.org
[mailto:owner-sv-ac@server.eda.org] On Behalf Of danielm
	Sent: Wednesday, April 02, 2008 2:42 AM
	To: sv-ac@server.eda-stds.org
	Subject: [sv-ac] assertion allowed variables

	LRM 1800-2005 says 17.4.2

	    "Static variables declared in programs, interfaces, or
clocking blocks can also be accessed."

	I see no reason why class static vars should be disallowed so
maybe the sentence should be changed to 

	     "Static variables declared in programs, interfaces,
clocking blocks, or classes can also be accessed."

	 

	Daniel Mlynek

	
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