RE: [sv-ac] assertion allowed variables

so need to be changed?

  _____  

From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Thursday, April 03, 2008 9:50 AM
To: danielm; Seligman, Erik
Cc: sv-ac@server.eda-stds.org
Subject: RE: [sv-ac] assertion allowed variables


It is the same in 16.5.2 of Draft 4.
 
Shalom


  _____  

From: Seligman, Erik [mailto:erik.seligman@intel.com] 
Sent: Wednesday, April 02, 2008 4:11 PM
To: danielm
Subject: RE: [sv-ac] assertion allowed variables


Hi Daniel-- 
Have you checked the correspondng section of 2008 draft 4?
 

  _____  

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of danielm
Sent: Wednesday, April 02, 2008 2:42 AM
To: sv-ac@server.eda-stds.org
Subject: [sv-ac] assertion allowed variables


LRM 1800-2005 says 17.4.2
    "Static variables declared in programs, interfaces, or clocking blocks
can also be accessed."

I see no reason why class static vars should be disallowed so maybe the
sentence should be changed to 

     "Static variables declared in programs, interfaces, clocking blocks, or
classes can also be accessed."

 

Daniel Mlynek


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