[sv-ac] RE: [SystemVerilog P1800 0001900]: Add new 'checker' construct to SVA

From: Korchemny, Dmitry <dmitry.korchemny_at_.....>
Date: Wed Mar 26 2008 - 04:16:25 PDT
Hi again,

Yes, indeed, it was not a good choice. E.g., Mantis requires all child
issues to be resolved before this one is. I will revert the
relationships, and will add a note what the real dependencies are.

Thanks,
Dmitry

-----Original Message-----
From: Korchemny, Dmitry 
Sent: Wednesday, March 26, 2008 1:09 PM
To: Bresticker, Shalom
Cc: 'Neil.Korpusik@Sun.COM'
Subject: RE: [SystemVerilog P1800 0001900]: Add new 'checker' construct
to SVA

Hi Shalom,

I can replace it when new categories are added, but I don't see any
other alternative now. I assume that "child" means that the current
proposal depends on the other one, and should the other proposal be
rejected, the current proposal would have to be modified. "Parent" is
symmetrical.

Thanks,
Dmitry

-----Original Message-----
From: Bresticker, Shalom 
Sent: Wednesday, March 26, 2008 12:37 PM
To: Korchemny, Dmitry
Cc: Neil.Korpusik@Sun.COM
Subject: RE: [SystemVerilog P1800 0001900]: Add new 'checker' construct
to SVA

Hi, Dmitry.

I don't think it is correct to categorize 1900 as a 'child' of issues
like 1648.

I think 'child' indicates either a sub-issue or a continuation or
extension. None of these are the case here. Having 1900 assuming that
1648 is approved is not enough to make 1900 a child of 1648.  

It would be nice if Mantis could indicate other types of dependency
relationships. Maybe Dave Rich can do it.

Shalom


> Relationships       ID      Summary
> ----------------------------------------------------------------------
> parent of           0002089 Allow checker construct (<a href="view....
> parent of           0002088 Allow Checker construct (<a href="view....
> parent of           0002093 Checker construct (<a href="view.php?id...
> parent of           0002111 Allow parameters in checkers
> parent of           0002110 Allow checkers in procedural for loops
> parent of           0002182 Elaborate VPI diagrams for checkers
> parent of           0002206 Random simulation of non-deterministic ...
> parent of           0002290 add signal valued system function model...
> related to          0001846 D3 21.13: add 1800-2008 to `begin_keywords
> child of            0001648 Default reset for assertions
> child of            0001682 Future value functions
> child of            0001683 Relax rules for building multiclocked p...
> child of            0001728 Introduce &quot;let&quot;statement
> child of            0001549 add missing formal argument types
> child of            0001681 Introduce global clocking
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Received on Wed Mar 26 04:20:23 2008

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