[sv-ac] RE: Updated version is ready

Hi Brad,

 

I think the default choice highly depends on an application. If you
write a checker for simulation, then a natural choice would be logic, if
for FV - then bit.

 

What do other people think?

 

Thanks,

Dmitry

 

________________________________

From: Brad Pierce [mailto:Brad.Pierce@synopsys.com] 
Sent: Thursday, February 21, 2008 6:46 PM
To: Korchemny, Dmitry; Bustan, Doron; eduard.cerny@synopsys.COM;
yaniv.fais@freescale.com; Manisha_Kulshrestha@mentor.com;
johan.martensson@jasper-da.com; piper@cadence.com; Seligman, Erik;
bassam.tabbara@synopsys.COM
Cc: Bresticker, Shalom
Subject: RE: Updated version is ready

 

Dmitry,

 

I don't care about consistency with the default of 'var', but only about
consistency with the typical user intent, to make things easy and
natural for users.

 

The purpose of defaults is to "go with the flow".  For example, if you
see a dirt path worn into the grass by pedestrians, that shows the
natural place to make a paved path.

 

If the typical user intent for checkvars is 'bit', then I don't see how
the default helps them.  For example, if the proposal and users continue
to say 'checkvar bit' all over the place, instead of simply 'checkvar',
then the default might as well not be there.

 

For users, a very popular advantage of the Verilog "look and feel" vs.
VHDL is that Verilog is felt to be "less verbose" than VHDL.   We need
to try to preserve that perceived advantage as we add new features.

 

-- Brad  

 

________________________________

From: Korchemny, Dmitry [mailto:dmitry.korchemny@intel.com] 
Sent: Thursday, February 21, 2008 8:19 AM
To: Bustan, Doron; eduard.cerny@synopsys.COM; yaniv.fais@freescale.com;
Manisha_Kulshrestha@mentor.com; johan.martensson@jasper-da.com;
piper@cadence.com; Seligman, Erik; bassam.tabbara@synopsys.COM
Cc: Bresticker, Shalom; Brad Pierce
Subject: Updated version is ready

Hi John,

 

I am attaching the updated version since Mantis is inaccessible. I will
deposit it into Mantis when it becomes available.

 

This version contains the following changes:

*	"free variables" --> "free checker variables" throughout the
text 
*	added the following  sentence to 16.18.6: "If a data type of a
checker variable is not specified, then the data type logic shall be
inferred." 

 

The changes shown with change bars in the document.

 

Thanks,

Dmitry

---------------------------------------------------------------------
Intel Israel (74) Limited
 
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.