Ed, > Regarding the inference of conditions from if and case > statements, this > is already in the LRM. The enabling condition is inferred from the > conditional path leading to the assertion and is placed in the > antecedent of an implication (not as part of the clock expression > because the values must be sampled the same way as the rest of the > variables in the assertion.) Right, understood. Many thanks. I'll do my homework on that. Time to stop meddling in things I don't understand :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sun Feb 17 07:09:24 2008
This archive was generated by hypermail 2.1.8 : Sun Feb 17 2008 - 07:09:49 PST