Shalom, > Regarding the loop, I think that Mantis 1995 specifies that the > assertion will be evaluated once for each iteration of the loop. Ah, sorry, as usual I am a few months behind the latest developments :-) So that means my assertion would have _eight_ executions, all behaving identically in the way I suggested, since my assertion does not depend on the loop variable. Inefficient, and misleading for coverage, but otherwise harmless. I would nevertheless like to ask the original question - whether it would be OK to infer a clock based on the flow of procedural execution through the "assert property". Thanks -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sun Feb 17 01:45:32 2008
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