RE: [sv-ac] call to vote on 1698

[Thomas Thatcher]

> I don't quite understand the new rules for inferring clocks from 
> procedural blocks.   For example:
>
> In the clock inference section, what does this phrase mean???
> 	"the event expression is maximal among those of these forms"

I too had difficulty in understanding this, and I could not see how
there would be any ambiguity if that requirement were to be deleted.

I think there are also some missed opportunities about 
disable (reset) inference, but perhaps that would be 
rather hard to define robustly.

So, here's a very stupid question from someone who's not an 
assertions expert:  Would it not be easier simply to define
an assertion's clock to occur whenever the flow of procedural
execution encounters its "assert property" statement?  That
rule would also allow you to enable and disable the clock based
on branches of conditionals, a very useful feature that is already
present in some formal tools:

  always @(posedge clock) begin
    assert property (!enable1 |=> $stable(Q1));  // A1
    assert property (!enable2 |=> $stable(Q2));  // A2
    if (enable1) begin
      assert property (Q1 == $past(D));          // A3
      Q1 <= D;
    end
    if (enable2) begin
      assert property (Q2 == $past(D));          // A4
      Q2 <= D;
    end
  end

In this example, the effective clocks are:
for A1 and A2, (posedge clock);
for A3, (posedge clock iff (enable1)); 
for A4, (posedge clock iff (enable2)).

I'm sure there must be some good reason why you don't wish 
to do that, but it looks a lot simpler to me....
Loops are OK, because (in synthesisable code) loops always
occur in zero time in the scheduler's Active region and therefore
will give rise to only one assertion evaluation (in Observed)
for each real clock event.  For example, here's a "count ones"
design, with an assertion to check its behaviour.  The assertion
is (unnecessarily) placed inside a loop, and so the flow of
procedural execution passes it eight times in each timeslot
where there is a clock.  However, that should give rise to
only one evaluation of the assertion.

  logic [7:0] y;
  logic [3:0] count;
  always @(posedge clock) begin : Count_Ones
    logic [3:0] n;
    n = 0;
    for (int i=7; i>=0; i++) begin
      n += y[i];
      assert property (count == $past($countones(y));
    end
    count <= n;
  end

Thanks, and apologies if this is wildly off.
-- 
Jonathan Bromley, Consultant

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