RE: [sv-ac] reflector unreliable -- call to vote on 2182

From: Bassam Tabbara <Bassam.Tabbara_at_.....>
Date: Mon Feb 11 2008 - 16:41:31 PST
Hi Tom,

(1) Yes should be 36.5.
- Your question: Partially covered by instance items yes. The other part
is 1503 will add property/sequence *decls* to scope diagram. 
(2) No, I think the bug is in the "module array" -- note how it is a
class (dotted enclosure) so obviously something is off with it... Please
file a mantis item with CC.
(3) These are the ports -- 1503.

Thx.
-Bassam.

-----Original Message-----
From: Thomas.Thatcher@Sun.COM [mailto:Thomas.Thatcher@Sun.COM] 
Sent: Monday, February 11, 2008 3:09 PM
To: john.havlicek@freescale.com
Cc: doron.bustan@intel.com; eduard.cerny@synopsys.COM;
yaniv.fais@freescale.com; dmitry.korchemny@intel.com;
Manisha_Kulshrestha@mentor.com; johan.martensson@jasper-da.com;
piper@cadence.com; erik.seligman@intel.com; bassam.tabbara@synopsys.COM;
sv-ac@eda.org; support@eda.org
Subject: Re: [sv-ac] reflector unreliable -- call to vote on 2182

I vote yes on 2182, with the following Friendly amendments:

1.  "36.4 Interface"  Shouldn't it be "36.5 Interface"?


I have a question that may turn into a friendly amendment:
The current diagrams for module and interface are being changed to add
checkers.  However, these diagrams don't show assertions, properties or
sequences.  Is there a reason for that?  Is that because assertions are
"Instance items"?

2.  The diagram for module shows a relationship between instance array
and module array with module.  Likewise the diagram for Interface shows
a relationship between instance array and interface array with
interface.  (like this:)

	Instance array <-------->> module
	                   |
	module array <------

However, the new checker diagram shows only a relationship between
instance array and checker

	instance array <----------->> checker

Shouldn't there be an arc for checker array as well?

	instance array <----------->> checker
	                       |
	checker array  <--------

3.  In the checkers diagram, there is an arc from checker to prop formal
decl.  Is "prop formal decl" the formal definition of a property?  Does
this arc also belong in the diagrams for module and interface as well?

Thanks,

Tom

John Havlicek wrote:
> Hi Folks:
> 
> The reflector is unreliable.
> 
> The message below was sent Wed Feb  6 14:53:20 -0600 2008.
> 
> J.H.
> 
> ======================================================================
> ============
> 
> Hi Folks:
> 
> This is the call to vote on the revised proposal for 2182.
> 
> The document on Mantis is
> 
>    2182checkersVPI_080122dk.pdf
> 
> Please vote if you are eligible.  See details below.
> 
> J.H.
> 
> ----------------------------------------------------------------------
> ------------
> Ballot on Mantis 2182
> 
> - Called on 2008-02-06, final ballots due by 2008-02-11 T 23:59-08:00.
> 
>  v[xxxxxxxxxxxxxxxxxxxxxxxx-xxxxxxxxxxxxxxxxxxxxxxxx-xx] Doron Bustan
(Intel)
>  v[xxxxxxxx--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx-x] Eduard Cerny
(Synopsys)     
>  n[-------------------------x-xxx---------x-x-xxx-x---x] Surrendra 
> Dudani (Synopsys)  
> v[x-xxxxxxxxx-xxxxxx-xxxxxxxxx-xx-xxxxx-xxx-xxx-------] Yaniv Fais 
> (Freescale)  t[xxxxxxx--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx] 
> John Havlicek (Freescale - Chair)  
> v[xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxrxxxxxxxxxxxxx-xxx] Dmitry 
> Korchemny (Intel - Co-Chair)  
> v[xxxxxxxx-xxxxxxxxx-xxx-x--xx--xxxxx----------xx-xxxx] Manisha 
> Kulshrestha (Mentor Graphics)  
> n[x-x-------------------------------------------------] Ah-Lam Lee 
> (Qualcomm)  n[---------------------------------xxxxx-------x-xx-x-] 
> Jiang Long (Mentor Graphics)  
> n[------------x------------x--xxx.....................] Joseph Lu 
> (Altera)  n[x--xxxxxxxxxxxxxxxxxxx..............................] 
> Johan Martensson (Jasper)
n[------------------------------x--x-xx--xx-xxxxxxx-x-] Hillel Miller
(Freescale)  v[xxxxxxxx-xxxx-xxxxxxxxxxxxxxxxxxx-xxxxxxxx-xxxxxxxxx]
Lisa Piper (Cadence)
v[xxxxxxxxx-x-x-xx-xxxxxxx-x-xxxxx-x..................] Erik Seligman
(Intel)  n[----------x-x----x--------xxxx-----xxxx-xx----------] Tej
Singh (Mentor Graphics)
v[xx-xxxxxx-x-xxxxxx--xxxxxxxx-xxxxxxxxxxxxxxxxxxxxxxx] Bassam Tabbara
(Synopsys)  v[xxxxxxxxxxxx-xxxxxxxxxxxxx-xxxxxxxxxx...............] Tom
Thatcher (Sun Microsystems)
>    |---------------------------------------------------- attendance on

> 2008-02-05
>  |------------------------------------------------------ voting 
> eligibility for this ballot
> |------------------------------------------------------- e-mail votes 
> |received
> 
>         Legend:
>                 x = attended
>                 - = missed
>                 r = represented
>                 . = not yet a member
>                 v = valid voter (2 out of last 3 or 3/4 overall)
>                 n = not a valid voter
>                 t = chair eligible to vote only to make or break a tie
> 
> 

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Received on Mon Feb 11 16:42:05 2008

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