RE: [sv-ac] call to vote on 1698

Hi Manisha,

the top-level property in an assertion must have a unique leading clock.

ed 

> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On 
> Behalf Of Kulshrestha, Manisha
> Sent: Tuesday, January 29, 2008 1:20 AM
> To: john.havlicek@freescale.com; sv-ac@eda.org
> Subject: RE: [sv-ac] call to vote on 1698
> 
> Hi,
> 
> I vote 'no' as I am confused about the following things in this
> proposal:
> 
> 1. It says: 
> Regardless where $past(x,,,@(posedge clk)) is called from (e.g. from
> the active, reactive, or observed regions), the RTL equivalent is:
> always @(posedge clk) past_variable <= $sampled(x);
> 
> Does that mean, the past variable is assigned in non-blocking 
> region ? I
> thought there was some proposal earlier where it was stated that past
> variable will be updated in the postponed region. I can not 
> remember the
> mantis number for that.
> 
> 2. It says: If used in an action block of a Multiclocked 
> assertion, the
> leading clock of the assertion is used. 
> But there may be multiple leading clocks in case of multiclocked
> assertion. E.g. 
> 
>   @(posedge clk1) P1 or @(posedge clk2) P2 where P1 and P2 
> are unclocked
> properties.
> 
> Thanks.
> Manisha
> 
> -----Original Message-----
> From: owner-sv-ac@server.eda.org 
> [mailto:owner-sv-ac@server.eda.org] On
> Behalf Of John Havlicek
> Sent: Thursday, January 24, 2008 8:40 AM
> To: sv-ac@server.eda.org
> Subject: [sv-ac] call to vote on 1698
> 
> Hi Folks:
> 
> This is the call to vote on 1698.
> 
> The proposal on Mantis is
> 
>    1698_sampled_value_functions_08_01_23.pdf
> 
> Please vote if you are eligible.  See the details below.
> 
> J.H.
> 
> --------------------------------------------------------------
> ----------
> ----------
> Ballot on Mantis 1698
> 
> - Called on 2008-01-23, final ballots due by 2008-01-28 T 23:59-08:00.
> 
>  v[xxxxxxxxxxxxxxxxxxxxxx-xxxxxxxxxxxxxxxxxxxxxxxx-xx] Doron Bustan
> (Intel)
>  v[xxxxxx--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx-x] Eduard Cerny
> (Synopsys)     
>  n[-----------------------x-xxx---------x-x-xxx-x---x] 
> Surrendra Dudani
> (Synopsys)
>  v[xxxxxxxxx-xxxxxx-xxxxxxxxx-xx-xxxxx-xxx-xxx-------] Yaniv Fais
> (Freescale)
>  t[xxxxx--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx] John Havlicek
> (Freescale - Chair)
>  v[xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxrxxxxxxxxxxxxx-xxx] Dmitry 
> Korchemny
> (Intel - Co-Chair)
>  v[xxxxxx-xxxxxxxxx-xxx-x--xx--xxxxx----------xx-xxxx] Manisha
> Kulshrestha (Mentor Graphics)
>  n[x-------------------------------------------------] Ah-Lam Lee
> (Qualcomm)
>  n[-------------------------------xxxxx-------x-xx-x-] Jiang Long
> (Mentor Graphics)
>  n[----------x------------x--xxx.....................] Joseph Lu
> (Altera)
>  v[-xxxxxxxxxxxxxxxxxxx..............................] Johan 
> Martensson
> (Jasper)
>  n[----------------------------x--x-xx--xx-xxxxxxx-x-] Hillel Miller
> (Freescale)
>  v[xxxxxx-xxxx-xxxxxxxxxxxxxxxxxxx-xxxxxxxx-xxxxxxxxx] Lisa Piper
> (Cadence)
>  v[xxxxxxx-x-x-xx-xxxxxxx-x-xxxxx-x..................] Erik Seligman
> (Intel)
>  n[--------x-x----x--------xxxx-----xxxx-xx----------] Tej 
> Singh (Mentor
> Graphics)
>  v[-xxxxxx-x-xxxxxx--xxxxxxxx-xxxxxxxxxxxxxxxxxxxxxxx] Bassam Tabbara
> (Synopsys)
>  v[xxxxxxxxxx-xxxxxxxxxxxxx-xxxxxxxxxx...............] Tom 
> Thatcher (Sun
> Microsystems)
>    |-------------------------------------------------- attendance on
> 2008-01-22
>  |---------------------------------------------------- voting
> eligibility for this ballot
> |----------------------------------------------------- e-mail votes
> received
> 
>         Legend:
>                 x = attended
>                 - = missed
>                 r = represented
>                 . = not yet a member
>                 v = valid voter (2 out of last 3 or 3/4 overall)
>                 n = not a valid voter
>                 t = chair eligible to vote only to make or break a tie
> 
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