[sv-ac] ballot result for 1698

From: John Havlicek <john.havlicek_at_.....>
Date: Tue Jan 29 2008 - 06:49:33 PST
Failed.  See below.

J.H.

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Ballot on Mantis 1698

- Called on 2008-01-23, final ballots due by 2008-01-28 T 23:59-08:00.

yv[xxxxxxxxxxxxxxxxxxxxxx-xxxxxxxxxxxxxxxxxxxxxxxx-xx] Doron Bustan (Intel)
yv[xxxxxx--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx-x] Eduard Cerny (Synopsys)     
 n[-----------------------x-xxx---------x-x-xxx-x---x] Surrendra Dudani (Synopsys)
yv[xxxxxxxxx-xxxxxx-xxxxxxxxx-xx-xxxxx-xxx-xxx-------] Yaniv Fais (Freescale)
 t[xxxxx--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx] John Havlicek (Freescale - Chair)
yv[xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxrxxxxxxxxxxxxx-xxx] Dmitry Korchemny (Intel - Co-Chair)
nv[xxxxxx-xxxxxxxxx-xxx-x--xx--xxxxx----------xx-xxxx] Manisha Kulshrestha (Mentor Graphics)
 n[x-------------------------------------------------] Ah-Lam Lee (Qualcomm)
 n[-------------------------------xxxxx-------x-xx-x-] Jiang Long (Mentor Graphics)
 n[----------x------------x--xxx.....................] Joseph Lu (Altera)
 v[-xxxxxxxxxxxxxxxxxxx..............................] Johan Martensson (Jasper)
 n[----------------------------x--x-xx--xx-xxxxxxx-x-] Hillel Miller (Freescale)
yv[xxxxxx-xxxx-xxxxxxxxxxxxxxxxxxx-xxxxxxxx-xxxxxxxxx] Lisa Piper (Cadence)
yv[xxxxxxx-x-x-xx-xxxxxxx-x-xxxxx-x..................] Erik Seligman (Intel)
 n[--------x-x----x--------xxxx-----xxxx-xx----------] Tej Singh (Mentor Graphics)
yv[-xxxxxx-x-xxxxxx--xxxxxxxx-xxxxxxxxxxxxxxxxxxxxxxx] Bassam Tabbara (Synopsys)
yv[xxxxxxxxxx-xxxxxxxxxxxxx-xxxxxxxxxx...............] Tom Thatcher (Sun Microsystems)
   |-------------------------------------------------- attendance on 2008-01-22
 |---------------------------------------------------- voting eligibility for this ballot
|----------------------------------------------------- e-mail votes received

        Legend:
                x = attended
                - = missed
                r = represented
                . = not yet a member
                v = valid voter (2 out of last 3 or 3/4 overall)
                n = not a valid voter
                t = chair eligible to vote only to make or break a tie

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Rationale for Negative Vote

[MK]

I vote 'no' as I am confused about the following things in this
proposal:

1. It says:=20
Regardless where $past(x,,,@(posedge clk)) is called from (e.g. from
the active, reactive, or observed regions), the RTL equivalent is:
always @(posedge clk) past_variable <=3D $sampled(x);

Does that mean, the past variable is assigned in non-blocking region ? I
thought there was some proposal earlier where it was stated that past
variable will be updated in the postponed region. I can not remember the
mantis number for that.

2. It says: If used in an action block of a Multiclocked assertion, the
leading clock of the assertion is used.=20
But there may be multiple leading clocks in case of multiclocked
assertion. E.g.=20

  @(posedge clk1) P1 or @(posedge clk2) P2 where P1 and P2 are unclocked
properties.

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Friendly Amendments

[BT]

Change first letter to lower case of "Always_ff" (2 of these) and "Multiclock".

[DK]

Page 3. "Always_ff" -> "always_ff"

Page 5. "In the example above, the inferred clock is "posedge clock iff
reset=3D=3D0"." I think that the quotes are redundant.

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Received on Tue Jan 29 06:50:13 2008

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