This misuses the term 'scalar'. In Verilog, a 1-bit vector is not a scalar, it is a 1-bit vector. A scalar in Verilog is by definition not a vector. How about "if the vector is just 1 bit"? Shalom > > 3. "Elaboration messages are used to indicate if the vector > is just a > > scalar,..." --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Jan 22 19:58:13 2008
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